- 15 Sep, 2021 3 commits
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Ilja Iskovs authored
Use an immediate zero operand for integer comparison when possible. This gives ~1% runtime performance improvement in some benchmarks on Neoverse N1. Change-Id: I727a8104f8e6ca3d122d6b5b8b3d38d7bdd76c47 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3158327Reviewed-by:
Zhi An Ng <zhin@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/main@{#76847}
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Leszek Swirski authored
Change-Id: I14400c0efea88b4bbb40aa2fbe9527dc9c67d3fb Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3160340 Auto-Submit: Leszek Swirski <leszeks@chromium.org> Commit-Queue: Leszek Swirski <leszeks@chromium.org> Reviewed-by:
Igor Sheludko <ishell@chromium.org> Cr-Commit-Position: refs/heads/main@{#76837}
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Lu Yahan authored
Bug: v8:11976 Change-Id: I19e1ef43f073c8155dbc2890de0f331782eb7aac Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3156588 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#76835}
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- 14 Sep, 2021 6 commits
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Ng Zhi An authored
Share the AVX and SSE4_1 code for Pextrd but delegate to base class for the pre-SSE4.1 code (via CRTP). Bug: v8:11589 Change-Id: Ic7709ccf7d9029829583c9287c1b0842ff11b799 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3160332Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76832}
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Milad Fa authored
r0 is used to indicate a value of "0" in which case only the ra() value gets used. Change-Id: I5ea5c51c1a652d042137c2d940818b93dac52492 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3159668Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/main@{#76830}
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Ng Zhi An authored
We need to support pre-SSE4.1 for Pinsrd. Share the AVX and SSE4_1 code, but delegate to base class for the pre-SSE4.1 code (via CRTP). Bug: v8:11589 Change-Id: I7563670174e44d8061182aefc311593d9578b0e4 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3159183Reviewed-by:
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Ng Zhi An authored
Pinsrb, Pinsrw was separately defined in ia32 and x64 macro assembler, move them into shared-macro-assembler. Pinsrd can be moved also, but is not as straightforward, move that in a future patch. Bug: v8:11589 Change-Id: Ib5c7517236e0c3fb7b9a4643f0a3ee8237ee6545 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3158681Reviewed-by:
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Leszek Swirski authored
CopyChars takes a count parameter, not an end parameter, so we can save some subtractions by passing in the count to WriteToFlat. Most of the time the start,end arguments into WriteToFlat are 0,length anyway, so this doesn't change a lot of places. Change-Id: I9587c7afce529218a16b728c0477b87569df8e21 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3157947Reviewed-by:
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Lu Yahan authored
If load imm32 using auipc/lui, for example load 0x7FFFFBF9, we should ensure imm32 + 0x800 is int32 Bug: v8:12171 Change-Id: I605ae9cad0b67cfd68d727ebdb3bcefea21904fb Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3141264Reviewed-by:
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- 13 Sep, 2021 7 commits
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Ng Zhi An authored
We move the implementation in Liftoff (which is the most general and handles AVX/SSE and also register aliasing) into shared-macro-assembler. Also consolidate SSE/AVX for ia32. No functionality change is expected. Bug: v8:11589 Bug: v8:11217 Change-Id: I64cc71791f04332dd3505055f4672430c2daf5ac Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131373Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76805}
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Ng Zhi An authored
Bug introduced In crrev.com/c/3150138. Fixed: v8:12220 Change-Id: I5cae11fdd43dc47dad0c8bf55daa6b925b629da0 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3158543Reviewed-by:
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Ng Zhi An authored
Move this from macro-assembler-x64 to shared-macro-assembler, and use this implementation for ia32 (TurboFan and Liftoff). Bug: v8:11589 Change-Id: If851560c8db1293924ca024725609c399c553a4a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3124099 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
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Junliang Yan authored
Change-Id: Icdef3916993e14e39ef9da70af128b9fde2d3b60 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3158323Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/main@{#76797}
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Lu Yahan authored
In riscv64, pc-relatice call need meet IsInt32(offset + 0x800), so max pcrelatice code range is 4094MB. Change-Id: Id3481483eb3131b5c08f22bde08206ee30cc25db Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3156585 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
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Lu Yahan authored
Change-Id: Ieeb5888efc068707766aef6ba6fc842c5deaaf9c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3146673 Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
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Lu Yahan authored
Bug: v8:12211 Change-Id: Ib12b2327bcbb93ef2556ce32a43a8b5749bbdd39 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3153835 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
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- 10 Sep, 2021 4 commits
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Ng Zhi An authored
This is a follow-up on https://crrev.com/c/3131374 to support more instructions, float32 sqrt, cmp, round, float64 cmp. Rename the opcodes since they are no longer SSE specific. Bug: v8:12148 Change-Id: Ie5f74bc1b4510092cbfbcb7e420ef82cb1c39a14 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3154983Reviewed-by:
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Junliang Yan authored
Change-Id: I1935a1ce50fcfb5f33511502367df624cc50a9df Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3155382Reviewed-by:
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Ng Zhi An authored
Move some AVX_OP into shared macro-assembler, for reuse by ia32 in future patches. Movlhps is also unused in x64, so remove it. Drive-by cleanup to use macro assembler helper Move to move 128-bit const into a XMMRegister. The change in liftoff-assembler-x64 is required because now the macro-assembler functions are defined in the base class, so even though we can use &TurboAssembler::Pcmpeqd to refer to that member function, it actually resolves to &SharedTurboAssembler::Pcmpeqd. Bug: v8:11589 Change-Id: Ie8f6a4dfd95b41192936f6e6be48c683042acec4 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3150138Reviewed-by:
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Clemens Backes authored
The {CountClearHalfWords} method is called whenever loading a constant into a register. It showed up with >0.5% in Liftoff compilation profiles. This CL refactors the method to return the number of *set* halfwords instead of *cleared* halfwords and avoids the loop in the implementation. This makes the method roughly twice as fast, and makes the code more readable. R=zhin@chromium.org Bug: v8:11879 Change-Id: I7da8160b3c045e5fc1e97fc0e575083b3920cb5b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3151962Reviewed-by:
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- 09 Sep, 2021 4 commits
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Ng Zhi An authored
With these accessors we can remove Assembler as a friend class. Drive-by cleanup to change DCHECK(!x || y) to DCHECK_IMPLIES(x, y). Change-Id: I74b7a23e85b50db93bbfe84fdfcc8563527f14d2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3144374Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76757}
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Ng Zhi An authored
This is similar to what is already done in x64, define a macro list for all the *sd instructions (prefix f2 0f), and use this macro list to define assembler functions and disassembly. Bug: v8:11879 Change-Id: Ia7fbd9fe7f07b72c04d82c81726b9673c40eb0de Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3125774 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
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Ng Zhi An authored
By delegating to the macro-assembler, emit AVX instructions for some float opcodes (float sqrt, round, conversions to and from int, extract/insert/load word). Since they now support AVX, we rename the instruction ops to remove the SSE prefix, changing it to be IA32. Bug: v8:12148 Change-Id: Ib488f03928756e7d85ab78e6cb28eb869e0641f9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131374Reviewed-by:
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Ng Zhi An authored
Change-Id: I51dee467f5b843e96ffccbe6e99ba203e8c3bf10 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3111266Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76754}
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- 08 Sep, 2021 9 commits
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Ng Zhi An authored
No functionality change is expected. Bug: v8:11217 Change-Id: I131d52794e4de24ec838cc23f15828edbfc656ff Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131372Reviewed-by:
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Ng Zhi An authored
Merge the SSE and AVX opcodes for I16x8Eq and I16x8GtS. We delegate to the macro-assembler to check for AVX. No functionality change is expected. Bug: v8:11217 Change-Id: I873b261d6f949bfc6755fe4c0e09b964a02c3684 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131371 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
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Ng Zhi An authored
Change-Id: I8afa821412ae248ddea990755404a9bf5f33184e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3125434Reviewed-by:
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Milad Fa authored
This CL takes advantage of the z15 `store byte reverse element` instructions to optimize Simd StoreLane opcodes. On the simulator we only run `store element` as reversing is not required. Change-Id: I723f6db535799470c46a1e298a9c1af7574ad5b6 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3144373Reviewed-by:
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Ng Zhi An authored
Combine the SSE and AVX versions, delegate to the macro-assembler functions to check for AVX support. Change Pand, Por, Pxor to generate the *ps version of the instruction when AVX is not supported. The *ps versions are 1 byte shorter, and have no performance difference on SSE-only processors. Bug: v8:11589 Bug: v8:11217 Change-Id: I9d51054359dcc909efcbb2c3d3bb63d399cd6721 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3124101Reviewed-by:
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Ng Zhi An authored
Do not require that dst == src1, this leaves more flexibility for the operands. We check in the macro-assembler if dst alias any of the input operands, then use vfma231/vfma132/vfma213 appropriately. Bug: v8:11659 Change-Id: I3644f5e0e75bd047d4e5f5b52d4234e54d329d15 Fixed: v8:11659 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131370 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
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Leszek Swirski authored
Fixed: v8:12192 Change-Id: Ifcb006bd1746e7bcf3b16c0e31e8cda9c920483c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3147590 Auto-Submit: Leszek Swirski <leszeks@chromium.org> Commit-Queue: Igor Sheludko <ishell@chromium.org> Reviewed-by:
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Zhao Jiazhong authored
We should use pc relative branch instruction rather than loading target address from memory for better performance. Besides, just like arm64, currently we assume that none of our relocation types are pc relative pointing outside the code buffer nor pc absolute pointing inside the code buffer. Change-Id: I9cce2e79c0afb00af967638405469f65df1deda2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3147314Reviewed-by:
Liu yu <liuyu@loongson.cn> Commit-Queue: Liu yu <liuyu@loongson.cn> Cr-Commit-Position: refs/heads/main@{#76721}
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Ng Zhi An authored
Bug: v8:11879 Change-Id: I02cfb6ca7cff418dc3e4ab422a1bc3437f0ea778 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3146075Reviewed-by:
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- 07 Sep, 2021 6 commits
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Ng Zhi An authored
Bug: v8:12094 Change-Id: Ibefce881cbfcd4445485197a4a2615bdf0599ada Fixed: v8:12094 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3123638 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
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Junliang Yan authored
Change-Id: Id37868f94a9ccebdee0530e9eb450c4acfa2f7c8 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3145414Reviewed-by:
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Lu Yahan authored
- Add vsetivli/I8x16Add/vl/vse8 - In Rvv, Vector regs is different from Float Regs. But in this cl, in order to facilitate modification, it is assumed that the vector register and float register share a set of register codes. - Because v0 is mask reg, we can't allocate it . And transfer float into vector reg, so i delete ft0 from AllocateReg. Bug: v8:11976 Change-Id: I66185d1f5ead985489bcbdf671b131f02a6bd7c2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3005768 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Thibaud Michaud <thibaudm@chromium.org> Reviewed-by:
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Patrick Thier authored
The receiver is now always included in the actual argument count and the formal parameter count. kDontAdaptArgumentsSentinel is changed from UINT16_MAX to 0 to preserve the maximum allowed declared parameters. The build flag activating the changes is not set for any architecture yet. Bug: v8:11112 Change-Id: I48a4969137949a1b4d1f47545209bb22b64e7e05 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3140608 Commit-Queue: Patrick Thier <pthier@chromium.org> Reviewed-by:
Leszek Swirski <leszeks@chromium.org> Reviewed-by:
Omer Katz <omerkatz@chromium.org> Reviewed-by:
Nico Hartmann <nicohartmann@chromium.org> Reviewed-by:
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Clemens Backes authored
This is a reland of 1786f8d7. It turned out that also x64 is broken, and only for TurboFan. Both is fixed now. Original change's description: > [arm64][liftoff] Fix trap handling on load lane > > This fixes the registered {protected_load_pc} to (always) point to the > actual load instruction. If {dst != src} we would emit a register move > before the load, and the trap handler would then not recognize the PC > where the signal occurs, leading to a segfault. > > R=thibaudm@chromium.org > > Bug: chromium:1242300, v8:12018 > Change-Id: I3ed2a8307e353fd85a7ddedf6ecb73e90a112d32 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3136454 > Reviewed-by: Thibaud Michaud <thibaudm@chromium.org> > Commit-Queue: Clemens Backes <clemensb@chromium.org> > Cr-Commit-Position: refs/heads/main@{#76642} Bug: chromium:1242300, v8:12018 Change-Id: I79284ab9815f5363f759569d98c8c4b52d48e738 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3140609Reviewed-by:
Maya Lekova <mslekova@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/main@{#76698}
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Junliang Yan authored
Change-Id: I1d743994115e659d3f6bf0ce17938b40d1467e5f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3144914Reviewed-by:
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- 06 Sep, 2021 1 commit
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Leszek Swirski authored
Remove the BaselineData intermediate structure for baseline code, and write the baseline Code object into the SharedFunctionInfo directly. We still need a pointer to the BytecodeArray/InterpreterData, so re-use the Code object's deoptimization data slot for this (baseline code doesn't have deoptimization data). A consequence of this is that the BytecodeArray pointer becomes immutable when there is baseline code. This means that we cannot install a debug BytecodeArray while baseline code is active (we have to flush it first), and we can't tier-up code with debug BytecodeArray to baseline. Change-Id: I53b93ec4d4c64b833603d7992f246982fcd97596 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3118548 Commit-Queue: Leszek Swirski <leszeks@chromium.org> Auto-Submit: Leszek Swirski <leszeks@chromium.org> Reviewed-by:
Camillo Bruni <cbruni@chromium.org> Reviewed-by:
Michael Lippautz <mlippautz@chromium.org> Reviewed-by:
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