[x64][ia32] Share pextrd code

Share the AVX and SSE4_1 code for Pextrd but delegate to base class for
the pre-SSE4.1 code (via CRTP).

Bug: v8:11589
Change-Id: Ic7709ccf7d9029829583c9287c1b0842ff11b799
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3160332Reviewed-by: Adam Klein <adamk@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/main@{#76832}

src/codegen/ia32/macro-assembler-ia32.cc

@@ -1588,21 +1588,12 @@ void TurboAssembler::Move(XMMRegister dst, uint64_t src) {
   }
 }
 
-void TurboAssembler::Pextrd(Register dst, XMMRegister src, uint8_t imm8) {
+void TurboAssembler::PextrdPreSse41(Register dst, XMMRegister src,
+                                    uint8_t imm8) {
   if (imm8 == 0) {
     Movd(dst, src);
     return;
   }
-  if (CpuFeatures::IsSupported(AVX)) {
-    CpuFeatureScope scope(this, AVX);
-    vpextrd(dst, src, imm8);
-    return;
-  }
-  if (CpuFeatures::IsSupported(SSE4_1)) {
-    CpuFeatureScope sse_scope(this, SSE4_1);
-    pextrd(dst, src, imm8);
-    return;
-  }
   // Without AVX or SSE, we can only have 64-bit values in xmm registers.
   // We don't have an xmm scratch register, so move the data via the stack. This
   // path is rarely required, so it's acceptable to be slow.

src/codegen/ia32/macro-assembler-ia32.h

@@ -336,7 +336,7 @@ class V8_EXPORT_PRIVATE TurboAssembler
     SharedTurboAssembler::Movhps(dst, src);
   }
 
-  void Pextrd(Register dst, XMMRegister src, uint8_t imm8);
+  void PextrdPreSse41(Register dst, XMMRegister src, uint8_t imm8);
   void PinsrdPreSse41(XMMRegister dst, Register src, uint8_t imm8,
                       uint32_t* load_pc_offset) {
     PinsrdPreSse41(dst, Operand(src), imm8, load_pc_offset);

src/codegen/shared-ia32-x64/macro-assembler-shared-ia32-x64.h

@@ -528,6 +528,24 @@ class V8_EXPORT_PRIVATE SharedTurboAssemblerBase : public SharedTurboAssembler {
   }
 #undef FLOAT_UNOP
 
+  void Pextrd(Register dst, XMMRegister src, uint8_t imm8) {
+    if (imm8 == 0) {
+      Movd(dst, src);
+      return;
+    }
+
+    if (CpuFeatures::IsSupported(AVX)) {
+      CpuFeatureScope scope(this, AVX);
+      vpextrd(dst, src, imm8);
+    } else if (CpuFeatures::IsSupported(SSE4_1)) {
+      CpuFeatureScope sse_scope(this, SSE4_1);
+      pextrd(dst, src, imm8);
+    } else {
+      DCHECK_LT(imm8, 2);
+      impl()->PextrdPreSse41(dst, src, imm8);
+    }
+  }
+
   template <typename Op>
   void Pinsrd(XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8,
               uint32_t* load_pc_offset = nullptr) {

src/codegen/x64/macro-assembler-x64.cc

@@ -2098,20 +2098,12 @@ void TurboAssembler::JumpCodeTObject(Register code, JumpMode jump_mode) {
   }
 }
 
-void TurboAssembler::Pextrd(Register dst, XMMRegister src, uint8_t imm8) {
+void TurboAssembler::PextrdPreSse41(Register dst, XMMRegister src,
+                                    uint8_t imm8) {
   if (imm8 == 0) {
     Movd(dst, src);
     return;
   }
-  if (CpuFeatures::IsSupported(AVX)) {
-    CpuFeatureScope scope(this, AVX);
-    vpextrd(dst, src, imm8);
-    return;
-  } else if (CpuFeatures::IsSupported(SSE4_1)) {
-    CpuFeatureScope sse_scope(this, SSE4_1);
-    pextrd(dst, src, imm8);
-    return;
-  }
   DCHECK_EQ(1, imm8);
   movq(dst, src);
   shrq(dst, Immediate(32));

src/codegen/x64/macro-assembler-x64.h

@@ -413,7 +413,7 @@ class V8_EXPORT_PRIVATE TurboAssembler
   void DebugBreak();
 
   // Non-SSE2 instructions.
-  void Pextrd(Register dst, XMMRegister src, uint8_t imm8);
+  void PextrdPreSse41(Register dst, XMMRegister src, uint8_t imm8);
 
   void PinsrdPreSse41(XMMRegister dst, Register src2, uint8_t imm8,
                       uint32_t* load_pc_offset = nullptr);