- 27 Mar, 2017 1 commit
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dusan.simicic authored
This patch adds support for MIPS SIMD (MSA) instructions in Assembler and Decoder (disassembler) classes. MSA instructions are implemented for both mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2740123004 Cr-Commit-Position: refs/heads/master@{#44148}
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- 17 Mar, 2017 1 commit
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jgruber authored
Default to the chromium-internal build config (instead of the more permissive no_chromium_code config). BUG=v8:5878 Review-Url: https://codereview.chromium.org/2758563002 Cr-Commit-Position: refs/heads/master@{#43909}
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- 30 Sep, 2016 1 commit
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balazs.kilvady authored
BUG= Review-Url: https://codereview.chromium.org/2374013004 Cr-Commit-Position: refs/heads/master@{#39904}
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- 23 Sep, 2016 1 commit
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balazs.kilvady authored
The running time of optdebug.quickcheck is improved by 8% while a more strict DCHECKing is kept in simulator. Review-Url: https://codereview.chromium.org/1349403003 Cr-Commit-Position: refs/heads/master@{#39667}
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- 14 Sep, 2016 1 commit
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Ilija.Pavlovic authored
Implementation MADD.S. MSUB.fmt, MADDF.fmt, MSUBF.fmt and corresponding tests for assembler and disassembler. TEST=cctest/test-assembler-mips[64], cctest/test-disasm-mips[64] BUG= Review-Url: https://codereview.chromium.org/2313623002 Cr-Commit-Position: refs/heads/master@{#39415}
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- 27 Jun, 2016 1 commit
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ivica.bogosavljevic authored
BUG= Review-Url: https://codereview.chromium.org/2069933003 Cr-Commit-Position: refs/heads/master@{#37295}
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- 28 Apr, 2016 1 commit
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ivica.bogosavljevic authored
Implement unaligned access instructions, and tests for corresponding instruction BUG= Review-Url: https://codereview.chromium.org/1902743002 Cr-Commit-Position: refs/heads/master@{#35873}
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- 19 Apr, 2016 1 commit
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akos.palfi authored
Port d412cfa2 BUG= Review URL: https://codereview.chromium.org/1899783003 Cr-Commit-Position: refs/heads/master@{#35613}
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- 11 Feb, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1691763002 Cr-Commit-Position: refs/heads/master@{#33913}
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- 08 Feb, 2016 1 commit
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ivica.bogosavljevic authored
Fix failures on MIPS simulator because incomplete handling of MTHC1 and MFHC1 in Fp32 mode Fix failures on older kernels that have problems with MTHC1 and MFHC1 in kernel FPU emulation Original issue's description: > Revert of MIPS: Add FPXX support to MIPS32R2 (patchset #3 > id:40001 of https://codereview.chromium.org/1586223004/ ) > > Reason for revert: > Revert patch due to a number of failures appearing on the > MIPS v8 simulator > > Original issue's description: >> MIPS: Add FPXX support to MIPS32R2 >> >> The JIT code generated by V8 is FPXX compliant >> when v8 compiled with FPXX flag. This allows the code to >> run in both FP=1 and FP=0 mode. It also alows v8 to be used >> as a library by both FP32 and FP64 binaries. >> >> BUG= >> >> Committed: https://crrev.com/95110dde666158a230a823fd50a68558ad772320 >> Cr-Commit-Position: refs/heads/master@{#33576} BUG= Review URL: https://codereview.chromium.org/1659883002 Cr-Commit-Position: refs/heads/master@{#33808}
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- 28 Jan, 2016 2 commits
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ivica.bogosavljevic authored
Revert of MIPS: Add FPXX support to MIPS32R2 (patchset #3 id:40001 of https://codereview.chromium.org/1586223004/ ) Reason for revert: Revert patch due to a number of failures appearing on the MIPS v8 simulator Original issue's description: > MIPS: Add FPXX support to MIPS32R2 > > The JIT code generated by V8 is FPXX compliant > when v8 compiled with FPXX flag. This allows the code to > run in both FP=1 and FP=0 mode. It also alows v8 to be used > as a library by both FP32 and FP64 binaries. > > BUG= > > Committed: https://crrev.com/95110dde666158a230a823fd50a68558ad772320 > Cr-Commit-Position: refs/heads/master@{#33576} TBR=paul.lind@imgtec.com,gergely.kis@imgtec.com,akos.palfi@imgtec.com,ilija.pavlovic@imgtec.com,marija.antic@imgtec.com,miran.karic@imgtec.com,balazs.kilvady@imgtec.com # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review URL: https://codereview.chromium.org/1646813003 Cr-Commit-Position: refs/heads/master@{#33583}
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ivica.bogosavljevic authored
The JIT code generated by V8 is FPXX compliant when v8 compiled with FPXX flag. This allows the code to run in both FP=1 and FP=0 mode. It also alows v8 to be used as a library by both FP32 and FP64 binaries. BUG= Review URL: https://codereview.chromium.org/1586223004 Cr-Commit-Position: refs/heads/master@{#33576}
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- 18 Jan, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1593713002 Cr-Commit-Position: refs/heads/master@{#33361}
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- 05 Jan, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1545013002 Cr-Commit-Position: refs/heads/master@{#33127}
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- 10 Dec, 2015 1 commit
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dusan.m.milosavljevic authored
TEST= BUG= Review URL: https://codereview.chromium.org/1508423002 Cr-Commit-Position: refs/heads/master@{#32749}
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- 02 Dec, 2015 1 commit
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ivica.bogosavljevic authored
MIPS R6 introduced new behavior for handling of NaN values for TRUNC, FLOOR, CEIL and CVT instructions. Adding support for the new behavior in MIPS and MIPS64 simulators. Fixing tests for MIPS and MIPS64 to align them with the new behavior. BUG= Review URL: https://codereview.chromium.org/1488613007 Cr-Commit-Position: refs/heads/master@{#32499}
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- 03 Nov, 2015 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1396133002 Cr-Commit-Position: refs/heads/master@{#31761}
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- 30 Sep, 2015 1 commit
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mstarzinger authored
This enables linter checking for "readability/namespace" violations during presubmit and instead marks the few known exceptions that we allow explicitly. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1371083003 Cr-Commit-Position: refs/heads/master@{#31019}
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- 04 Sep, 2015 1 commit
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balazs.kilvady authored
The patch decreases the calls of huge switch instructions making the DecodeType*() functions to work in one phase and optimizing Instruction::InstructionType(). Speed gain in release full check is about 33% (6:13 s -> 4:09 s) and in optdebug full test is about 50% (12:29 -> 6:17) BUG= Review URL: https://codereview.chromium.org/1310883005 Cr-Commit-Position: refs/heads/master@{#30596}
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- 19 Jun, 2015 1 commit
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Ilija.Pavlovic authored
Added: JIC, BEQZC, JIALC, LDPC, LWPC, ALUIPC, ADDIUPC, ALIGN/DAILGN, LWUPC, AUIPC, BC, BALC. Additional fixed compact branch offset. TEST=test-assembler-mips[64]/r6_align, r6_dalign, r6_aluipc, r6_lwpc, r6_jic, r6_beqzc, r6_jialc, r6_addiupc, r6_ldpc, r6_lwupc, r6_auipc, r6_bc, r6_balc BUG= Review URL: https://codereview.chromium.org/1195793002 Cr-Commit-Position: refs/heads/master@{#29143}
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- 22 May, 2015 1 commit
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1145223002 Cr-Commit-Position: refs/heads/master@{#28595}
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- 19 May, 2015 1 commit
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1147493002 Cr-Commit-Position: refs/heads/master@{#28472}
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- 14 May, 2015 2 commits
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paul.lind authored
Reason for revert: Simulator test failures in RunChangeFloat64ToInt.., RunChangeTaggedToInt32, div-mul-minus-one Original issue's description: > Implement assembler, disassembler tests for all instructions for mips32 > and mips64. Additionally, add missing single precision float instructions > for r2 and r6 architecture variants in assembler, simulator and disassembler > with corresponding tests. BUG= Review URL: https://codereview.chromium.org/1143473003 Cr-Commit-Position: refs/heads/master@{#28404}
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1119203003 Cr-Commit-Position: refs/heads/master@{#28402}
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- 05 May, 2015 1 commit
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dusan.milosavljevic authored
- Add long branche mode for FPU branches. - Fix FPU branches for unordered conditions. - Provide FPU [un]ordered condition negation schema. TEST=mjsunit/miror-objects, constant-folding-2, external-array BUG= Review URL: https://codereview.chromium.org/1120753010 Cr-Commit-Position: refs/heads/master@{#28241}
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- 30 Apr, 2015 1 commit
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Djordje.Pesic authored
Added rounding according to fcsr, CVT_W_D and RINT.D instruction in assembler, dissasembler and simulator and wrote appropiate tests. BUG= Review URL: https://codereview.chromium.org/1108583003 Cr-Commit-Position: refs/heads/master@{#28143}
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- 17 Feb, 2015 1 commit
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balazs.kilvady authored
Fix compilation problem with android toolchain. Added new INTERNAL_REFERENCE_ENCODED RelocInfo type to differentiate MIPS existing use of internal references in instructions from the new raw pointer reference needed for dd(Label*). BUG= TEST=cctest/test-assembler-mips/jump_tables1, cctest/test-assembler-mips/jump_tables2, cctest/test-assembler-mips/jump_tables3, cctest/test-run-machops/RunSwitch1 Review URL: https://codereview.chromium.org/935593002 Cr-Commit-Position: refs/heads/master@{#26693}
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- 16 Feb, 2015 1 commit
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machenbach authored
Revert of MIPS: Fix 'Assembler support for internal references.' (patchset #1 id:1 of https://codereview.chromium.org/922043005/) Reason for revert: Breaks http://build.chromium.org/p/chromium.fyi/builders/Android%20MIPS%20Builder%20(dbg) Original issue's description: > MIPS: Fix 'Assembler support for internal references.' > > Added new INTERNAL_REFERENCE_ENCODED RelocInfo type to differentiate MIPS existing use of internal references in instructions from the new raw pointer reference needed for dd(Label*). > > BUG= > TEST=cctest/test-assembler-mips/jump_tables1, cctest/test-assembler-mips/jump_tables2, cctest/test-assembler-mips/jump_tables3, cctest/test-run-machops/RunSwitch1 > > Committed: https://crrev.com/244ac6de8316259bc5878480e05348a369c08e2f > Cr-Commit-Position: refs/heads/master@{#26651} TBR=danno@chromium.org,bmeurer@chromium.org,jkummerow@chromium.org,paul.lind@imgtec.com,gergely.kis@imgtec.com,akos.palfi@imgtec.com,dusan.milosavljevic@imgtec.com,balazs.kilvady@imgtec.com NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review URL: https://codereview.chromium.org/934623003 Cr-Commit-Position: refs/heads/master@{#26675}
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- 15 Feb, 2015 1 commit
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balazs.kilvady authored
Added new INTERNAL_REFERENCE_ENCODED RelocInfo type to differentiate MIPS existing use of internal references in instructions from the new raw pointer reference needed for dd(Label*). BUG= TEST=cctest/test-assembler-mips/jump_tables1, cctest/test-assembler-mips/jump_tables2, cctest/test-assembler-mips/jump_tables3, cctest/test-run-machops/RunSwitch1 Review URL: https://codereview.chromium.org/922043005 Cr-Commit-Position: refs/heads/master@{#26651}
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- 09 Feb, 2015 1 commit
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balazs.kilvady authored
Port 49cbe537 BUG= Review URL: https://codereview.chromium.org/911623003 Cr-Commit-Position: refs/heads/master@{#26534}
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- 26 Jan, 2015 1 commit
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balazs.kilvady authored
Change stack handling to clarify the usage of reserved MIPS argument slots for mips32. BUG= Review URL: https://codereview.chromium.org/867183003 Cr-Commit-Position: refs/heads/master@{#26279}
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- 08 Dec, 2014 1 commit
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Benedikt Meurer authored
TBR=machenbach@chromium.org Review URL: https://codereview.chromium.org/783913003 Cr-Commit-Position: refs/heads/master@{#25699}
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- 09 Oct, 2014 1 commit
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dusan.milosavljevic@imgtec.com authored
TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/618193005 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24486 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 12 Aug, 2014 1 commit
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dusan.milosavljevic@imgtec.com authored
Fixing gclient runhooks failure caused by reverted commit r23050. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/467583002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23088 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 11 Aug, 2014 4 commits
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machenbach@chromium.org authored
This reverts commit r23050 for breaking runhooks on chromium. See e.g.: http://build.chromium.org/p/client.v8/builders/Chrome%20Linux%20Perf/builds/1438/steps/runhooks/logs/stdio TBR=jochen@chromium.org Review URL: https://codereview.chromium.org/458983003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23053 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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dusan.milosavljevic@imgtec.com authored
Original commit r23028 breaks ARM64 build due to conflicting FP64 symbolic constant definition in src/globals.h and src/arm64/constants-arm64.h. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/457313003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23050 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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jochen@chromium.org authored
Breaks compilation of ARM64. | Additional summary: | - Introduce fp64 fpu mode into mips32 port required for r6. | - Implement runtime detections for fpu mode and arch. revision to preserve | compatibility with previous architecture revisions. | | TEST= | BUG= | R=jkummerow@chromium.org, paul.lind@imgtec.com | | Review URL: https://codereview.chromium.org/453043002 BUG=none LOG=n TBR=jkummerow@chromium.org Review URL: https://codereview.chromium.org/458193002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23030 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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dusan.milosavljevic@imgtec.com authored
Additional summary: - Introduce fp64 fpu mode into mips32 port required for r6. - Implement runtime detections for fpu mode and arch. revision to preserve compatibility with previous architecture revisions. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/453043002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23028 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 04 Aug, 2014 1 commit
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bmeurer@chromium.org authored
This way we don't clash with the ASSERT* macros defined by GoogleTest, and we are one step closer to being able to replace our homegrown base/ with base/ from Chrome. R=jochen@chromium.org, svenpanne@chromium.org Review URL: https://codereview.chromium.org/430503007 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22812 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 05 Jun, 2014 1 commit
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titzer@chromium.org authored
R=jkummerow@google.com, jkummerow@chromium.org BUG= Review URL: https://codereview.chromium.org/313283003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21685 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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