Commit dd23044a authored by mbrandy's avatar mbrandy Committed by Commit bot

PPC: [crankshaft] Fix Math.min(0, 0)

Port 0d59772b

Original commit message:
    for the special case where the same register is used as both left and
    right input.

R=jkummerow@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1698903002

Cr-Commit-Position: refs/heads/master@{#34004}
parent 3b980234
...@@ -1960,14 +1960,18 @@ void LCodeGen::DoMathMinMax(LMathMinMax* instr) { ...@@ -1960,14 +1960,18 @@ void LCodeGen::DoMathMinMax(LMathMinMax* instr) {
__ bne(&return_left); // left == right != 0. __ bne(&return_left); // left == right != 0.
// At this point, both left and right are either 0 or -0. // At this point, both left and right are either 0 or -0.
// N.B. The following works because +0 + -0 == +0
if (operation == HMathMinMax::kMathMin) { if (operation == HMathMinMax::kMathMin) {
// For min we want logical-or of sign bit: -(-L + -R) // Min: The algorithm is: -((-L) + (-R)), which in case of L and R being
// different registers is most efficiently expressed as -((-L) - R).
__ fneg(left_reg, left_reg); __ fneg(left_reg, left_reg);
__ fsub(result_reg, left_reg, right_reg); if (left_reg.is(right_reg)) {
__ fadd(result_reg, left_reg, right_reg);
} else {
__ fsub(result_reg, left_reg, right_reg);
}
__ fneg(result_reg, result_reg); __ fneg(result_reg, result_reg);
} else { } else {
// For max we want logical-and of sign bit: (L + R) // Max: The following works because +0 + -0 == +0
__ fadd(result_reg, left_reg, right_reg); __ fadd(result_reg, left_reg, right_reg);
} }
__ b(&done); __ b(&done);
......
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