[mips][wasm-simd] Implement i64x2 signed compares

Besides, implement i64x2 signed compares in liftoff.

Port: a38039a7
Port: b57a0d19

Bug: v8:11415
Change-Id: I18e9bdbf346daacbb53595e504f14a32aedcfc07
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2711725Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Auto-Submit: Liu yu <liuyu@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#72887}

src/compiler/backend/mips/code-generator-mips.cc

@@ -2293,6 +2293,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                i.OutputSimd128Register());
       break;
     }
+    case kMipsI64x2GtS: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ clt_s_d(i.OutputSimd128Register(), i.InputSimd128Register(1),
+                 i.InputSimd128Register(0));
+      break;
+    }
+    case kMipsI64x2GeS: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ cle_s_d(i.OutputSimd128Register(), i.InputSimd128Register(1),
+                 i.InputSimd128Register(0));
+      break;
+    }
     case kMipsI64x2SConvertI32x4Low: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       Simd128Register dst = i.OutputSimd128Register();

src/compiler/backend/mips/instruction-codes-mips.h

@@ -173,6 +173,8 @@ namespace compiler {
   V(MipsI64x2BitMask)              \
   V(MipsI64x2Eq)                   \
   V(MipsI64x2Ne)                   \
+  V(MipsI64x2GtS)                  \
+  V(MipsI64x2GeS)                  \
   V(MipsI64x2SConvertI32x4Low)     \
   V(MipsI64x2SConvertI32x4High)    \
   V(MipsI64x2UConvertI32x4Low)     \

src/compiler/backend/mips/instruction-scheduler-mips.cc

@@ -76,6 +76,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsI64x2BitMask:
     case kMipsI64x2Eq:
     case kMipsI64x2Ne:
+    case kMipsI64x2GtS:
+    case kMipsI64x2GeS:
     case kMipsI64x2SConvertI32x4Low:
     case kMipsI64x2SConvertI32x4High:
     case kMipsI64x2UConvertI32x4Low:

src/compiler/backend/mips/instruction-selector-mips.cc

@@ -2196,6 +2196,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I64x2Add, kMipsI64x2Add)                             \
   V(I64x2Sub, kMipsI64x2Sub)                             \
   V(I64x2Mul, kMipsI64x2Mul)                             \
+  V(I64x2GtS, kMipsI64x2GtS)                             \
+  V(I64x2GeS, kMipsI64x2GeS)                             \
   V(I64x2SConvertI32x4Low, kMipsI64x2SConvertI32x4Low)   \
   V(I64x2SConvertI32x4High, kMipsI64x2SConvertI32x4High) \
   V(I64x2UConvertI32x4Low, kMipsI64x2UConvertI32x4Low)   \

src/compiler/backend/mips64/code-generator-mips64.cc

@@ -2435,6 +2435,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                i.OutputSimd128Register());
       break;
     }
+    case kMips64I64x2GtS: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ clt_s_d(i.OutputSimd128Register(), i.InputSimd128Register(1),
+                 i.InputSimd128Register(0));
+      break;
+    }
+    case kMips64I64x2GeS: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ cle_s_d(i.OutputSimd128Register(), i.InputSimd128Register(1),
+                 i.InputSimd128Register(0));
+      break;
+    }
     case kMips64I64x2SConvertI32x4Low: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       Simd128Register dst = i.OutputSimd128Register();

src/compiler/backend/mips64/instruction-codes-mips64.h

@@ -226,6 +226,8 @@ namespace compiler {
   V(Mips64I64x2BitMask)                      \
   V(Mips64I64x2Eq)                           \
   V(Mips64I64x2Ne)                           \
+  V(Mips64I64x2GtS)                          \
+  V(Mips64I64x2GeS)                          \
   V(Mips64I64x2SConvertI32x4Low)             \
   V(Mips64I64x2SConvertI32x4High)            \
   V(Mips64I64x2UConvertI32x4Low)             \

src/compiler/backend/mips64/instruction-scheduler-mips64.cc

@@ -104,6 +104,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64I64x2BitMask:
     case kMips64I64x2Eq:
     case kMips64I64x2Ne:
+    case kMips64I64x2GtS:
+    case kMips64I64x2GeS:
     case kMips64I64x2SConvertI32x4Low:
     case kMips64I64x2SConvertI32x4High:
     case kMips64I64x2UConvertI32x4Low:

src/compiler/backend/mips64/instruction-selector-mips64.cc

@@ -2934,6 +2934,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I64x2Add, kMips64I64x2Add)                           \
   V(I64x2Sub, kMips64I64x2Sub)                           \
   V(I64x2Mul, kMips64I64x2Mul)                           \
+  V(I64x2GtS, kMips64I64x2GtS)                           \
+  V(I64x2GeS, kMips64I64x2GeS)                           \
   V(F32x4Add, kMips64F32x4Add)                           \
   V(F32x4AddHoriz, kMips64F32x4AddHoriz)                 \
   V(F32x4Sub, kMips64F32x4Sub)                           \

src/wasm/baseline/mips/liftoff-assembler-mips.h

@@ -2384,6 +2384,16 @@ void LiftoffAssembler::emit_i64x2_mul(LiftoffRegister dst, LiftoffRegister lhs,
   bailout(kSimd, "emit_i64x2_mul");
 }
 
+void LiftoffAssembler::emit_i64x2_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
+                                       LiftoffRegister rhs) {
+  bailout(kSimd, "emit_i64x2_gt_s");
+}
+
+void LiftoffAssembler::emit_i64x2_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
+                                       LiftoffRegister rhs) {
+  bailout(kSimd, "emit_i64x2_ge_s");
+}
+
 void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst,
                                       LiftoffRegister src) {
   bailout(kSimd, "emit_f32x4_abs");

src/wasm/baseline/mips64/liftoff-assembler-mips64.h

@@ -2384,6 +2384,16 @@ void LiftoffAssembler::emit_i64x2_mul(LiftoffRegister dst, LiftoffRegister lhs,
   mulv_d(dst.fp().toW(), lhs.fp().toW(), rhs.fp().toW());
 }
 
+void LiftoffAssembler::emit_i64x2_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
+                                       LiftoffRegister rhs) {
+  clt_s_d(dst.fp().toW(), rhs.fp().toW(), lhs.fp().toW());
+}
+
+void LiftoffAssembler::emit_i64x2_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
+                                       LiftoffRegister rhs) {
+  cle_s_d(dst.fp().toW(), rhs.fp().toW(), lhs.fp().toW());
+}
+
 void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst,
                                       LiftoffRegister src) {
   bclri_w(dst.fp().toW(), src.fp().toW(), 31);