assembler-ia32.cc 66.1 KB
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
// OF THE POSSIBILITY OF SUCH DAMAGE.

// The original source code covered by the above license above has been modified
// significantly by Google Inc.
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// Copyright 2012 the V8 project authors. All rights reserved.
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#include "src/ia32/assembler-ia32.h"

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#include <cstring>

#if V8_TARGET_ARCH_IA32

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#if V8_LIBC_MSVCRT
#include <intrin.h>  // _xgetbv()
#endif
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#if V8_OS_MACOSX
#include <sys/sysctl.h>
#endif
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#include "src/base/bits.h"
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#include "src/base/cpu.h"
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#include "src/disassembler.h"
#include "src/macro-assembler.h"
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#include "src/v8.h"
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namespace v8 {
namespace internal {
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// -----------------------------------------------------------------------------
// Implementation of CpuFeatures

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namespace {

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#if !V8_LIBC_MSVCRT

V8_INLINE uint64_t _xgetbv(unsigned int xcr) {
  unsigned eax, edx;
  // Check xgetbv; this uses a .byte sequence instead of the instruction
  // directly because older assemblers do not include support for xgetbv and
  // there is no easy way to conditionally compile based on the assembler
  // used.
  __asm__ volatile(".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
  return static_cast<uint64_t>(eax) | (static_cast<uint64_t>(edx) << 32);
}

#define _XCR_XFEATURE_ENABLED_MASK 0

#endif  // !V8_LIBC_MSVCRT


bool OSHasAVXSupport() {
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#if V8_OS_MACOSX
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  // Mac OS X up to 10.9 has a bug where AVX transitions were indeed being
  // caused by ISRs, so we detect that here and disable AVX in that case.
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  char buffer[128];
  size_t buffer_size = arraysize(buffer);
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  int ctl_name[] = {CTL_KERN, KERN_OSRELEASE};
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  if (sysctl(ctl_name, 2, buffer, &buffer_size, nullptr, 0) != 0) {
    V8_Fatal(__FILE__, __LINE__, "V8 failed to get kernel version");
  }
  // The buffer now contains a string of the form XX.YY.ZZ, where
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  // XX is the major kernel version component.
  char* period_pos = strchr(buffer, '.');
  DCHECK_NOT_NULL(period_pos);
  *period_pos = '\0';
  long kernel_version_major = strtol(buffer, nullptr, 10);  // NOLINT
  if (kernel_version_major <= 13) return false;
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#endif  // V8_OS_MACOSX
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  // Check whether OS claims to support AVX.
  uint64_t feature_mask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
  return (feature_mask & 0x6) == 0x6;
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}

}  // namespace


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void CpuFeatures::ProbeImpl(bool cross_compile) {
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  base::CPU cpu;
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  CHECK(cpu.has_sse2());  // SSE2 support is mandatory.
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  CHECK(cpu.has_cmov());  // CMOV support is mandatory.
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  // Only use statically determined features for cross compile (snapshot).
  if (cross_compile) return;
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  if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
  if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
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  if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
      OSHasAVXSupport()) {
    supported_ |= 1u << AVX;
  }
  if (cpu.has_fma3() && FLAG_enable_fma3 && cpu.has_osxsave() &&
      OSHasAVXSupport()) {
    supported_ |= 1u << FMA3;
  }
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  if (cpu.has_bmi1() && FLAG_enable_bmi1) supported_ |= 1u << BMI1;
  if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2;
  if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT;
  if (cpu.has_popcnt() && FLAG_enable_popcnt) supported_ |= 1u << POPCNT;
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  if (strcmp(FLAG_mcpu, "auto") == 0) {
    if (cpu.is_atom()) supported_ |= 1u << ATOM;
  } else if (strcmp(FLAG_mcpu, "atom") == 0) {
    supported_ |= 1u << ATOM;
  }
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}


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void CpuFeatures::PrintTarget() { }
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void CpuFeatures::PrintFeatures() {
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  printf(
      "SSE3=%d SSE4_1=%d AVX=%d FMA3=%d BMI1=%d BMI2=%d LZCNT=%d POPCNT=%d "
      "ATOM=%d\n",
      CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSE4_1),
      CpuFeatures::IsSupported(AVX), CpuFeatures::IsSupported(FMA3),
      CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2),
      CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT),
      CpuFeatures::IsSupported(ATOM));
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}
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// -----------------------------------------------------------------------------
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// Implementation of Displacement

void Displacement::init(Label* L, Type type) {
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  DCHECK(!L->is_bound());
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  int next = 0;
  if (L->is_linked()) {
    next = L->pos();
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    DCHECK(next > 0);  // Displacements must be at positions > 0
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  }
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  // Ensure that we _never_ overflow the next field.
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  DCHECK(NextField::is_valid(Assembler::kMaximalBufferSize));
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  data_ = NextField::encode(next) | TypeField::encode(type);
}
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// -----------------------------------------------------------------------------
// Implementation of RelocInfo


const int RelocInfo::kApplyMask =
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    RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
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    1 << RelocInfo::INTERNAL_REFERENCE | 1 << RelocInfo::CODE_AGE_SEQUENCE |
    RelocInfo::kDebugBreakSlotMask;
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bool RelocInfo::IsCodedSpecially() {
  // The deserializer needs to know whether a pointer is specially coded.  Being
  // specially coded on IA32 means that it is a relative address, as used by
  // branch instructions.  These are also the ones that need changing when a
  // code object moves.
  return (1 << rmode_) & kApplyMask;
}


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bool RelocInfo::IsInConstantPool() {
  return false;
}

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Address RelocInfo::wasm_memory_reference() {
  DCHECK(IsWasmMemoryReference(rmode_));
  return Memory::Address_at(pc_);
}

uint32_t RelocInfo::wasm_memory_size_reference() {
  DCHECK(IsWasmMemorySizeReference(rmode_));
  return Memory::uint32_at(pc_);
}

void RelocInfo::update_wasm_memory_reference(
    Address old_base, Address new_base, uint32_t old_size, uint32_t new_size,
    ICacheFlushMode icache_flush_mode) {
  DCHECK(IsWasmMemoryReference(rmode_) || IsWasmMemorySizeReference(rmode_));
  if (IsWasmMemoryReference(rmode_)) {
    Address updated_reference;
    DCHECK(old_base <= wasm_memory_reference() &&
           wasm_memory_reference() < old_base + old_size);
    updated_reference = new_base + (wasm_memory_reference() - old_base);
    DCHECK(new_base <= updated_reference &&
           updated_reference < new_base + new_size);
    Memory::Address_at(pc_) = updated_reference;
  } else if (IsWasmMemorySizeReference(rmode_)) {
    uint32_t updated_size_reference;
    DCHECK(wasm_memory_size_reference() <= old_size);
    updated_size_reference =
        new_size + (wasm_memory_size_reference() - old_size);
    DCHECK(updated_size_reference <= new_size);
    Memory::uint32_at(pc_) = updated_size_reference;
  } else {
    UNREACHABLE();
  }
  if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
    Assembler::FlushICache(isolate_, pc_, sizeof(int32_t));
  }
}
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// -----------------------------------------------------------------------------
// Implementation of Operand

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Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
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  // [base + disp/r]
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  if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
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    // [base]
    set_modrm(0, base);
    if (base.is(esp)) set_sib(times_1, esp, base);
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  } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
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    // [base + disp8]
    set_modrm(1, base);
    if (base.is(esp)) set_sib(times_1, esp, base);
    set_disp8(disp);
  } else {
    // [base + disp/r]
    set_modrm(2, base);
    if (base.is(esp)) set_sib(times_1, esp, base);
    set_dispr(disp, rmode);
  }
}


Operand::Operand(Register base,
                 Register index,
                 ScaleFactor scale,
                 int32_t disp,
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                 RelocInfo::Mode rmode) {
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  DCHECK(!index.is(esp));  // illegal addressing mode
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  // [base + index*scale + disp/r]
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  if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
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    // [base + index*scale]
    set_modrm(0, esp);
    set_sib(scale, index, base);
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  } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
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    // [base + index*scale + disp8]
    set_modrm(1, esp);
    set_sib(scale, index, base);
    set_disp8(disp);
  } else {
    // [base + index*scale + disp/r]
    set_modrm(2, esp);
    set_sib(scale, index, base);
    set_dispr(disp, rmode);
  }
}


Operand::Operand(Register index,
                 ScaleFactor scale,
                 int32_t disp,
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                 RelocInfo::Mode rmode) {
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  DCHECK(!index.is(esp));  // illegal addressing mode
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  // [index*scale + disp/r]
  set_modrm(0, esp);
  set_sib(scale, index, ebp);
  set_dispr(disp, rmode);
}


bool Operand::is_reg(Register reg) const {
  return ((buf_[0] & 0xF8) == 0xC0)  // addressing mode is register only.
      && ((buf_[0] & 0x07) == reg.code());  // register codes match.
}

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bool Operand::is_reg_only() const {
  return (buf_[0] & 0xF8) == 0xC0;  // Addressing mode is register only.
}


Register Operand::reg() const {
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  DCHECK(is_reg_only());
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  return Register::from_code(buf_[0] & 0x07);
}


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// -----------------------------------------------------------------------------
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// Implementation of Assembler.
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// Emit a single byte. Must always be inlined.
#define EMIT(x)                                 \
  *pc_++ = (x)


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#ifdef GENERATED_CODE_COVERAGE
static void InitCoverageLog();
#endif

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Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
    : AssemblerBase(isolate, buffer, buffer_size),
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      positions_recorder_(this) {
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  // Clear the buffer in debug mode unless it was provided by the
  // caller in which case we can't be sure it's okay to overwrite
  // existing code in it; see CodePatcher::CodePatcher(...).
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#ifdef DEBUG
  if (own_buffer_) {
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    memset(buffer_, 0xCC, buffer_size_);  // int3
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  }
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#endif
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  reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
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#ifdef GENERATED_CODE_COVERAGE
  InitCoverageLog();
#endif
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}


void Assembler::GetCode(CodeDesc* desc) {
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  // Finalize code (at this point overflow() may be true, but the gap ensures
  // that we are still not overlapping instructions and relocation info).
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  reloc_info_writer.Finish();
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  DCHECK(pc_ <= reloc_info_writer.pos());  // No overlap.
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  // Set up code descriptor.
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  desc->buffer = buffer_;
  desc->buffer_size = buffer_size_;
  desc->instr_size = pc_offset();
  desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
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  desc->origin = this;
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  desc->constant_pool_size = 0;
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}


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void Assembler::Align(int m) {
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  DCHECK(base::bits::IsPowerOfTwo32(m));
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  int mask = m - 1;
  int addr = pc_offset();
  Nop((m - (addr & mask)) & mask);
}


bool Assembler::IsNop(Address addr) {
  Address a = addr;
  while (*a == 0x66) a++;
  if (*a == 0x90) return true;
  if (a[0] == 0xf && a[1] == 0x1f) return true;
  return false;
}


void Assembler::Nop(int bytes) {
  EnsureSpace ensure_space(this);

  // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf
  while (bytes > 0) {
    switch (bytes) {
      case 2:
        EMIT(0x66);
      case 1:
        EMIT(0x90);
        return;
      case 3:
        EMIT(0xf);
        EMIT(0x1f);
        EMIT(0);
        return;
      case 4:
        EMIT(0xf);
        EMIT(0x1f);
        EMIT(0x40);
        EMIT(0);
        return;
      case 6:
        EMIT(0x66);
      case 5:
        EMIT(0xf);
        EMIT(0x1f);
        EMIT(0x44);
        EMIT(0);
        EMIT(0);
        return;
      case 7:
        EMIT(0xf);
        EMIT(0x1f);
        EMIT(0x80);
        EMIT(0);
        EMIT(0);
        EMIT(0);
        EMIT(0);
        return;
      default:
      case 11:
        EMIT(0x66);
        bytes--;
      case 10:
        EMIT(0x66);
        bytes--;
      case 9:
        EMIT(0x66);
        bytes--;
      case 8:
        EMIT(0xf);
        EMIT(0x1f);
        EMIT(0x84);
        EMIT(0);
        EMIT(0);
        EMIT(0);
        EMIT(0);
        EMIT(0);
        bytes -= 8;
    }
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  }
}


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void Assembler::CodeTargetAlign() {
  Align(16);  // Preferred alignment of jump targets on ia32.
}


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void Assembler::cpuid() {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xA2);
}


void Assembler::pushad() {
  EnsureSpace ensure_space(this);
  EMIT(0x60);
}


void Assembler::popad() {
  EnsureSpace ensure_space(this);
  EMIT(0x61);
}


void Assembler::pushfd() {
  EnsureSpace ensure_space(this);
  EMIT(0x9C);
}


void Assembler::popfd() {
  EnsureSpace ensure_space(this);
  EMIT(0x9D);
}


void Assembler::push(const Immediate& x) {
  EnsureSpace ensure_space(this);
  if (x.is_int8()) {
    EMIT(0x6a);
    EMIT(x.x_);
  } else {
    EMIT(0x68);
    emit(x);
  }
}


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void Assembler::push_imm32(int32_t imm32) {
  EnsureSpace ensure_space(this);
  EMIT(0x68);
  emit(imm32);
}


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void Assembler::push(Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x50 | src.code());
}


void Assembler::push(const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xFF);
  emit_operand(esi, src);
}


void Assembler::pop(Register dst) {
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  DCHECK(reloc_info_writer.last_pc() != NULL);
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  EnsureSpace ensure_space(this);
  EMIT(0x58 | dst.code());
}


void Assembler::pop(const Operand& dst) {
  EnsureSpace ensure_space(this);
  EMIT(0x8F);
  emit_operand(eax, dst);
}


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void Assembler::enter(const Immediate& size) {
  EnsureSpace ensure_space(this);
  EMIT(0xC8);
  emit_w(size);
  EMIT(0);
}


void Assembler::leave() {
  EnsureSpace ensure_space(this);
  EMIT(0xC9);
}


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void Assembler::mov_b(Register dst, const Operand& src) {
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  CHECK(dst.is_byte_register());
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  EnsureSpace ensure_space(this);
  EMIT(0x8A);
  emit_operand(dst, src);
}


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void Assembler::mov_b(const Operand& dst, const Immediate& src) {
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  EnsureSpace ensure_space(this);
  EMIT(0xC6);
  emit_operand(eax, dst);
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  EMIT(static_cast<int8_t>(src.x_));
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}


void Assembler::mov_b(const Operand& dst, Register src) {
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  CHECK(src.is_byte_register());
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  EnsureSpace ensure_space(this);
  EMIT(0x88);
  emit_operand(src, dst);
}


void Assembler::mov_w(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x8B);
  emit_operand(dst, src);
}


void Assembler::mov_w(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x89);
  emit_operand(src, dst);
}


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void Assembler::mov_w(const Operand& dst, const Immediate& src) {
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  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0xC7);
  emit_operand(eax, dst);
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  EMIT(static_cast<int8_t>(src.x_ & 0xff));
  EMIT(static_cast<int8_t>(src.x_ >> 8));
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}


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void Assembler::mov(Register dst, int32_t imm32) {
  EnsureSpace ensure_space(this);
  EMIT(0xB8 | dst.code());
  emit(imm32);
}


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void Assembler::mov(Register dst, const Immediate& x) {
  EnsureSpace ensure_space(this);
  EMIT(0xB8 | dst.code());
  emit(x);
}


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void Assembler::mov(Register dst, Handle<Object> handle) {
  EnsureSpace ensure_space(this);
  EMIT(0xB8 | dst.code());
  emit(handle);
}


void Assembler::mov(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x8B);
  emit_operand(dst, src);
}


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void Assembler::mov(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x89);
  EMIT(0xC0 | src.code() << 3 | dst.code());
}


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void Assembler::mov(const Operand& dst, const Immediate& x) {
  EnsureSpace ensure_space(this);
  EMIT(0xC7);
  emit_operand(eax, dst);
  emit(x);
}


void Assembler::mov(const Operand& dst, Handle<Object> handle) {
  EnsureSpace ensure_space(this);
  EMIT(0xC7);
  emit_operand(eax, dst);
  emit(handle);
}


void Assembler::mov(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x89);
  emit_operand(src, dst);
}


void Assembler::movsx_b(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xBE);
  emit_operand(dst, src);
}


void Assembler::movsx_w(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xBF);
  emit_operand(dst, src);
}


void Assembler::movzx_b(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xB6);
  emit_operand(dst, src);
}


void Assembler::movzx_w(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xB7);
  emit_operand(dst, src);
}


void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
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  // Opcode: 0f 40 + cc /r.
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  EMIT(0x0F);
  EMIT(0x40 + cc);
  emit_operand(dst, src);
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}


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void Assembler::cld() {
  EnsureSpace ensure_space(this);
  EMIT(0xFC);
}


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void Assembler::rep_movs() {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0xA5);
}


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void Assembler::rep_stos() {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0xAB);
}


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void Assembler::stos() {
  EnsureSpace ensure_space(this);
  EMIT(0xAB);
}


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void Assembler::xchg(Register dst, Register src) {
  EnsureSpace ensure_space(this);
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  if (src.is(eax) || dst.is(eax)) {  // Single-byte encoding.
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    EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
  } else {
    EMIT(0x87);
    EMIT(0xC0 | src.code() << 3 | dst.code());
  }
}


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void Assembler::xchg(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x87);
  emit_operand(dst, src);
}

720 721 722 723 724 725 726 727 728 729 730 731
void Assembler::xchg_b(Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  EMIT(0x86);
  emit_operand(reg, op);
}

void Assembler::xchg_w(Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x87);
  emit_operand(reg, op);
}
732

733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759
void Assembler::lock() {
  EnsureSpace ensure_space(this);
  EMIT(0xF0);
}

void Assembler::cmpxchg(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xB1);
  emit_operand(src, dst);
}

void Assembler::cmpxchg_b(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xB0);
  emit_operand(src, dst);
}

void Assembler::cmpxchg_w(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0xB1);
  emit_operand(src, dst);
}

760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779
void Assembler::adc(Register dst, int32_t imm32) {
  EnsureSpace ensure_space(this);
  emit_arith(2, Operand(dst), Immediate(imm32));
}


void Assembler::adc(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x13);
  emit_operand(dst, src);
}


void Assembler::add(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x03);
  emit_operand(dst, src);
}


780 781 782 783 784 785 786
void Assembler::add(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x01);
  emit_operand(src, dst);
}


787
void Assembler::add(const Operand& dst, const Immediate& x) {
788
  DCHECK(reloc_info_writer.last_pc() != NULL);
789 790 791 792 793 794
  EnsureSpace ensure_space(this);
  emit_arith(0, dst, x);
}


void Assembler::and_(Register dst, int32_t imm32) {
795 796 797 798 799
  and_(dst, Immediate(imm32));
}


void Assembler::and_(Register dst, const Immediate& x) {
800
  EnsureSpace ensure_space(this);
801
  emit_arith(4, Operand(dst), x);
802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820
}


void Assembler::and_(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x23);
  emit_operand(dst, src);
}


void Assembler::and_(const Operand& dst, const Immediate& x) {
  EnsureSpace ensure_space(this);
  emit_arith(4, dst, x);
}


void Assembler::and_(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x21);
821
  emit_operand(src, dst);
822 823
}

824 825
void Assembler::cmpb(const Operand& op, Immediate imm8) {
  DCHECK(imm8.is_int8() || imm8.is_uint8());
826
  EnsureSpace ensure_space(this);
827 828 829 830 831 832
  if (op.is_reg(eax)) {
    EMIT(0x3C);
  } else {
    EMIT(0x80);
    emit_operand(edi, op);  // edi == 7
  }
833
  emit_b(imm8);
834 835 836
}


837
void Assembler::cmpb(const Operand& op, Register reg) {
838
  CHECK(reg.is_byte_register());
839 840
  EnsureSpace ensure_space(this);
  EMIT(0x38);
841
  emit_operand(reg, op);
842 843 844
}


845
void Assembler::cmpb(Register reg, const Operand& op) {
846
  CHECK(reg.is_byte_register());
847 848
  EnsureSpace ensure_space(this);
  EMIT(0x3A);
849
  emit_operand(reg, op);
850 851 852
}


853
void Assembler::cmpw(const Operand& op, Immediate imm16) {
854
  DCHECK(imm16.is_int16());
855 856 857 858 859 860 861
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x81);
  emit_operand(edi, op);
  emit_w(imm16);
}

862 863 864 865 866 867 868 869 870 871 872 873 874
void Assembler::cmpw(Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x39);
  emit_operand(reg, op);
}

void Assembler::cmpw(const Operand& op, Register reg) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x3B);
  emit_operand(reg, op);
}
875

876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893
void Assembler::cmp(Register reg, int32_t imm32) {
  EnsureSpace ensure_space(this);
  emit_arith(7, Operand(reg), Immediate(imm32));
}


void Assembler::cmp(Register reg, Handle<Object> handle) {
  EnsureSpace ensure_space(this);
  emit_arith(7, Operand(reg), Immediate(handle));
}


void Assembler::cmp(Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  EMIT(0x3B);
  emit_operand(reg, op);
}

894 895 896 897 898
void Assembler::cmp(const Operand& op, Register reg) {
  EnsureSpace ensure_space(this);
  EMIT(0x39);
  emit_operand(reg, op);
}
899 900 901 902 903 904 905

void Assembler::cmp(const Operand& op, const Immediate& imm) {
  EnsureSpace ensure_space(this);
  emit_arith(7, op, imm);
}


906 907 908 909 910 911
void Assembler::cmp(const Operand& op, Handle<Object> handle) {
  EnsureSpace ensure_space(this);
  emit_arith(7, op, Immediate(handle));
}


912
void Assembler::cmpb_al(const Operand& op) {
913
  EnsureSpace ensure_space(this);
914 915
  EMIT(0x38);  // CMP r/m8, r8
  emit_operand(eax, op);  // eax has same code as register al.
916 917
}

918 919

void Assembler::cmpw_ax(const Operand& op) {
920
  EnsureSpace ensure_space(this);
921 922 923
  EMIT(0x66);
  EMIT(0x39);  // CMP r/m16, r16
  emit_operand(eax, op);  // eax has same code as register ax.
924 925 926
}


927
void Assembler::dec_b(Register dst) {
928
  CHECK(dst.is_byte_register());
929 930 931 932 933 934
  EnsureSpace ensure_space(this);
  EMIT(0xFE);
  EMIT(0xC8 | dst.code());
}


935 936 937 938 939 940 941
void Assembler::dec_b(const Operand& dst) {
  EnsureSpace ensure_space(this);
  EMIT(0xFE);
  emit_operand(ecx, dst);
}


942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960
void Assembler::dec(Register dst) {
  EnsureSpace ensure_space(this);
  EMIT(0x48 | dst.code());
}


void Assembler::dec(const Operand& dst) {
  EnsureSpace ensure_space(this);
  EMIT(0xFF);
  emit_operand(ecx, dst);
}


void Assembler::cdq() {
  EnsureSpace ensure_space(this);
  EMIT(0x99);
}


961 962 963 964 965 966 967 968
void Assembler::idiv(const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
  emit_operand(edi, src);
}


void Assembler::div(const Operand& src) {
969 970
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
971
  emit_operand(esi, src);
972 973 974
}


975 976 977 978 979 980 981
void Assembler::imul(Register reg) {
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
  EMIT(0xE8 | reg.code());
}


982 983 984 985 986 987 988 989 990
void Assembler::imul(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xAF);
  emit_operand(dst, src);
}


void Assembler::imul(Register dst, Register src, int32_t imm32) {
991 992 993 994 995
  imul(dst, Operand(src), imm32);
}


void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
996 997 998
  EnsureSpace ensure_space(this);
  if (is_int8(imm32)) {
    EMIT(0x6B);
999
    emit_operand(dst, src);
1000 1001 1002
    EMIT(imm32);
  } else {
    EMIT(0x69);
1003
    emit_operand(dst, src);
1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042
    emit(imm32);
  }
}


void Assembler::inc(Register dst) {
  EnsureSpace ensure_space(this);
  EMIT(0x40 | dst.code());
}


void Assembler::inc(const Operand& dst) {
  EnsureSpace ensure_space(this);
  EMIT(0xFF);
  emit_operand(eax, dst);
}


void Assembler::lea(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x8D);
  emit_operand(dst, src);
}


void Assembler::mul(Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
  EMIT(0xE0 | src.code());
}


void Assembler::neg(Register dst) {
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
  EMIT(0xD8 | dst.code());
}


1043 1044 1045 1046 1047 1048 1049
void Assembler::neg(const Operand& dst) {
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
  emit_operand(ebx, dst);
}


1050 1051 1052 1053 1054 1055 1056
void Assembler::not_(Register dst) {
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
  EMIT(0xD0 | dst.code());
}


1057 1058 1059 1060 1061 1062 1063
void Assembler::not_(const Operand& dst) {
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
  emit_operand(edx, dst);
}


1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085
void Assembler::or_(Register dst, int32_t imm32) {
  EnsureSpace ensure_space(this);
  emit_arith(1, Operand(dst), Immediate(imm32));
}


void Assembler::or_(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0B);
  emit_operand(dst, src);
}


void Assembler::or_(const Operand& dst, const Immediate& x) {
  EnsureSpace ensure_space(this);
  emit_arith(1, dst, x);
}


void Assembler::or_(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x09);
1086
  emit_operand(src, dst);
1087 1088 1089 1090 1091
}


void Assembler::rcl(Register dst, uint8_t imm8) {
  EnsureSpace ensure_space(this);
1092
  DCHECK(is_uint5(imm8));  // illegal shift count
1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
  if (imm8 == 1) {
    EMIT(0xD1);
    EMIT(0xD0 | dst.code());
  } else {
    EMIT(0xC1);
    EMIT(0xD0 | dst.code());
    EMIT(imm8);
  }
}


1104 1105
void Assembler::rcr(Register dst, uint8_t imm8) {
  EnsureSpace ensure_space(this);
1106
  DCHECK(is_uint5(imm8));  // illegal shift count
1107 1108 1109 1110 1111 1112 1113 1114 1115 1116
  if (imm8 == 1) {
    EMIT(0xD1);
    EMIT(0xD8 | dst.code());
  } else {
    EMIT(0xC1);
    EMIT(0xD8 | dst.code());
    EMIT(imm8);
  }
}

1117

1118
void Assembler::ror(const Operand& dst, uint8_t imm8) {
1119
  EnsureSpace ensure_space(this);
1120
  DCHECK(is_uint5(imm8));  // illegal shift count
1121 1122
  if (imm8 == 1) {
    EMIT(0xD1);
1123
    emit_operand(ecx, dst);
1124 1125
  } else {
    EMIT(0xC1);
1126
    emit_operand(ecx, dst);
1127 1128 1129 1130
    EMIT(imm8);
  }
}

1131

1132
void Assembler::ror_cl(const Operand& dst) {
1133 1134
  EnsureSpace ensure_space(this);
  EMIT(0xD3);
1135
  emit_operand(ecx, dst);
1136 1137
}

1138

1139
void Assembler::sar(const Operand& dst, uint8_t imm8) {
1140
  EnsureSpace ensure_space(this);
1141
  DCHECK(is_uint5(imm8));  // illegal shift count
1142 1143
  if (imm8 == 1) {
    EMIT(0xD1);
1144
    emit_operand(edi, dst);
1145 1146
  } else {
    EMIT(0xC1);
1147
    emit_operand(edi, dst);
1148 1149 1150 1151 1152
    EMIT(imm8);
  }
}


1153
void Assembler::sar_cl(const Operand& dst) {
1154 1155
  EnsureSpace ensure_space(this);
  EMIT(0xD3);
1156
  emit_operand(edi, dst);
1157 1158 1159 1160 1161 1162 1163 1164
}

void Assembler::sbb(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x1B);
  emit_operand(dst, src);
}

1165 1166 1167 1168 1169 1170 1171 1172
void Assembler::shld(Register dst, Register src, uint8_t shift) {
  DCHECK(is_uint5(shift));
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xA4);
  emit_operand(src, Operand(dst));
  EMIT(shift);
}
1173

1174
void Assembler::shld_cl(Register dst, Register src) {
1175 1176 1177
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xA5);
1178
  emit_operand(src, Operand(dst));
1179 1180 1181
}


1182
void Assembler::shl(const Operand& dst, uint8_t imm8) {
1183
  EnsureSpace ensure_space(this);
1184
  DCHECK(is_uint5(imm8));  // illegal shift count
1185 1186
  if (imm8 == 1) {
    EMIT(0xD1);
1187
    emit_operand(esp, dst);
1188 1189
  } else {
    EMIT(0xC1);
1190
    emit_operand(esp, dst);
1191 1192 1193 1194 1195
    EMIT(imm8);
  }
}


1196
void Assembler::shl_cl(const Operand& dst) {
1197 1198
  EnsureSpace ensure_space(this);
  EMIT(0xD3);
1199
  emit_operand(esp, dst);
1200 1201
}

1202
void Assembler::shr(const Operand& dst, uint8_t imm8) {
1203
  EnsureSpace ensure_space(this);
1204
  DCHECK(is_uint5(imm8));  // illegal shift count
1205 1206
  if (imm8 == 1) {
    EMIT(0xD1);
1207
    emit_operand(ebp, dst);
1208 1209
  } else {
    EMIT(0xC1);
1210
    emit_operand(ebp, dst);
1211 1212
    EMIT(imm8);
  }
1213 1214 1215
}


1216
void Assembler::shr_cl(const Operand& dst) {
1217
  EnsureSpace ensure_space(this);
1218
  EMIT(0xD3);
1219
  emit_operand(ebp, dst);
1220 1221
}

1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236
void Assembler::shrd(Register dst, Register src, uint8_t shift) {
  DCHECK(is_uint5(shift));
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xAC);
  emit_operand(dst, Operand(src));
  EMIT(shift);
}

void Assembler::shrd_cl(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xAD);
  emit_operand(src, dst);
}
1237

1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253
void Assembler::sub(const Operand& dst, const Immediate& x) {
  EnsureSpace ensure_space(this);
  emit_arith(5, dst, x);
}


void Assembler::sub(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x2B);
  emit_operand(dst, src);
}


void Assembler::sub(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x29);
1254
  emit_operand(src, dst);
1255 1256 1257 1258
}


void Assembler::test(Register reg, const Immediate& imm) {
1259 1260
  if (imm.is_uint8()) {
    test_b(reg, imm);
1261 1262 1263
    return;
  }

1264
  EnsureSpace ensure_space(this);
1265 1266 1267 1268
  // This is not using emit_arith because test doesn't support
  // sign-extension of 8-bit operands.
  if (reg.is(eax)) {
    EMIT(0xA9);
1269
  } else {
1270 1271
    EMIT(0xF7);
    EMIT(0xC0 | reg.code());
1272
  }
1273
  emit(imm);
1274 1275 1276 1277 1278 1279 1280 1281 1282 1283
}


void Assembler::test(Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  EMIT(0x85);
  emit_operand(reg, op);
}


1284
void Assembler::test_b(Register reg, const Operand& op) {
1285
  CHECK(reg.is_byte_register());
1286 1287 1288 1289 1290 1291
  EnsureSpace ensure_space(this);
  EMIT(0x84);
  emit_operand(reg, op);
}


1292
void Assembler::test(const Operand& op, const Immediate& imm) {
1293 1294 1295 1296
  if (op.is_reg_only()) {
    test(op.reg(), imm);
    return;
  }
1297 1298
  if (imm.is_uint8()) {
    return test_b(op, imm);
1299
  }
1300 1301 1302 1303 1304 1305
  EnsureSpace ensure_space(this);
  EMIT(0xF7);
  emit_operand(eax, op);
  emit(imm);
}

1306 1307
void Assembler::test_b(Register reg, Immediate imm8) {
  DCHECK(imm8.is_uint8());
1308 1309 1310 1311 1312
  EnsureSpace ensure_space(this);
  // Only use test against byte for registers that have a byte
  // variant: eax, ebx, ecx, and edx.
  if (reg.is(eax)) {
    EMIT(0xA8);
1313
    emit_b(imm8);
1314
  } else if (reg.is_byte_register()) {
1315
    emit_arith_b(0xF6, 0xC0, reg, static_cast<uint8_t>(imm8.x_));
1316
  } else {
1317
    EMIT(0x66);
1318 1319
    EMIT(0xF7);
    EMIT(0xC0 | reg.code());
1320
    emit_w(imm8);
1321 1322 1323
  }
}

1324
void Assembler::test_b(const Operand& op, Immediate imm8) {
1325 1326
  if (op.is_reg_only()) {
    test_b(op.reg(), imm8);
1327 1328
    return;
  }
1329 1330 1331
  EnsureSpace ensure_space(this);
  EMIT(0xF6);
  emit_operand(eax, op);
1332
  emit_b(imm8);
1333 1334
}

1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367
void Assembler::test_w(Register reg, Immediate imm16) {
  DCHECK(imm16.is_int16() || imm16.is_uint16());
  EnsureSpace ensure_space(this);
  if (reg.is(eax)) {
    EMIT(0xA9);
    emit_w(imm16);
  } else {
    EMIT(0x66);
    EMIT(0xF7);
    EMIT(0xc0 | reg.code());
    emit_w(imm16);
  }
}

void Assembler::test_w(Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x85);
  emit_operand(reg, op);
}

void Assembler::test_w(const Operand& op, Immediate imm16) {
  DCHECK(imm16.is_int16() || imm16.is_uint16());
  if (op.is_reg_only()) {
    test_w(op.reg(), imm16);
    return;
  }
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0xF7);
  emit_operand(eax, op);
  emit_w(imm16);
}
1368

1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381
void Assembler::xor_(Register dst, int32_t imm32) {
  EnsureSpace ensure_space(this);
  emit_arith(6, Operand(dst), Immediate(imm32));
}


void Assembler::xor_(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x33);
  emit_operand(dst, src);
}


1382
void Assembler::xor_(const Operand& dst, Register src) {
1383 1384
  EnsureSpace ensure_space(this);
  EMIT(0x31);
1385
  emit_operand(src, dst);
1386 1387 1388 1389 1390 1391 1392 1393 1394
}


void Assembler::xor_(const Operand& dst, const Immediate& x) {
  EnsureSpace ensure_space(this);
  emit_arith(6, dst, x);
}


1395 1396 1397 1398 1399 1400 1401 1402
void Assembler::bt(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xA3);
  emit_operand(src, dst);
}


1403 1404 1405 1406 1407 1408 1409 1410
void Assembler::bts(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xAB);
  emit_operand(src, dst);
}


1411 1412 1413 1414 1415 1416 1417 1418
void Assembler::bsr(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xBD);
  emit_operand(dst, src);
}


1419 1420 1421 1422 1423 1424 1425 1426
void Assembler::bsf(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xBC);
  emit_operand(dst, src);
}


1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446
void Assembler::hlt() {
  EnsureSpace ensure_space(this);
  EMIT(0xF4);
}


void Assembler::int3() {
  EnsureSpace ensure_space(this);
  EMIT(0xCC);
}


void Assembler::nop() {
  EnsureSpace ensure_space(this);
  EMIT(0x90);
}


void Assembler::ret(int imm16) {
  EnsureSpace ensure_space(this);
1447
  DCHECK(is_uint16(imm16));
1448 1449 1450 1451 1452 1453 1454 1455 1456 1457
  if (imm16 == 0) {
    EMIT(0xC3);
  } else {
    EMIT(0xC2);
    EMIT(imm16 & 0xFF);
    EMIT((imm16 >> 8) & 0xFF);
  }
}


1458 1459 1460 1461 1462 1463 1464
void Assembler::ud2() {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x0B);
}


1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498
// Labels refer to positions in the (to be) generated code.
// There are bound, linked, and unused labels.
//
// Bound labels refer to known positions in the already
// generated code. pos() is the position the label refers to.
//
// Linked labels refer to unknown positions in the code
// to be generated; pos() is the position of the 32bit
// Displacement of the last instruction using the label.


void Assembler::print(Label* L) {
  if (L->is_unused()) {
    PrintF("unused label\n");
  } else if (L->is_bound()) {
    PrintF("bound label to %d\n", L->pos());
  } else if (L->is_linked()) {
    Label l = *L;
    PrintF("unbound label");
    while (l.is_linked()) {
      Displacement disp = disp_at(&l);
      PrintF("@ %d ", l.pos());
      disp.print();
      PrintF("\n");
      disp.next(&l);
    }
  } else {
    PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
  }
}


void Assembler::bind_to(Label* L, int pos) {
  EnsureSpace ensure_space(this);
1499
  DCHECK(0 <= pos && pos <= pc_offset());  // must have a valid binding position
1500 1501 1502
  while (L->is_linked()) {
    Displacement disp = disp_at(L);
    int fixup_pos = L->pos();
1503 1504 1505 1506
    if (disp.type() == Displacement::CODE_ABSOLUTE) {
      long_at_put(fixup_pos, reinterpret_cast<int>(buffer_ + pos));
      internal_reference_positions_.push_back(fixup_pos);
    } else if (disp.type() == Displacement::CODE_RELATIVE) {
1507 1508
      // Relative to Code* heap object pointer.
      long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1509 1510
    } else {
      if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1511
        DCHECK(byte_at(fixup_pos - 1) == 0xE9);  // jmp expected
1512
      }
1513
      // Relative address, relative to point after address.
1514 1515
      int imm32 = pos - (fixup_pos + sizeof(int32_t));
      long_at_put(fixup_pos, imm32);
1516 1517 1518
    }
    disp.next(L);
  }
1519 1520 1521 1522
  while (L->is_near_linked()) {
    int fixup_pos = L->near_link_pos();
    int offset_to_next =
        static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1523
    DCHECK(offset_to_next <= 0);
1524 1525
    // Relative address, relative to point after address.
    int disp = pos - fixup_pos - sizeof(int8_t);
1526
    CHECK(0 <= disp && disp <= 127);
1527 1528 1529 1530 1531 1532 1533
    set_byte_at(fixup_pos, disp);
    if (offset_to_next < 0) {
      L->link_to(fixup_pos + offset_to_next, Label::kNear);
    } else {
      L->UnuseNear();
    }
  }
1534 1535 1536 1537 1538 1539
  L->bind_to(pos);
}


void Assembler::bind(Label* L) {
  EnsureSpace ensure_space(this);
1540
  DCHECK(!L->is_bound());  // label can only be bound once
1541 1542 1543 1544 1545
  bind_to(L, pc_offset());
}


void Assembler::call(Label* L) {
1546
  positions_recorder()->WriteRecordedPositions();
1547 1548 1549 1550
  EnsureSpace ensure_space(this);
  if (L->is_bound()) {
    const int long_size = 5;
    int offs = L->pos() - pc_offset();
1551
    DCHECK(offs <= 0);
1552
    // 1110 1000 #32-bit disp.
1553 1554 1555
    EMIT(0xE8);
    emit(offs - long_size);
  } else {
1556
    // 1110 1000 #32-bit disp.
1557 1558 1559 1560 1561 1562
    EMIT(0xE8);
    emit_disp(L, Displacement::OTHER);
  }
}


1563
void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1564
  positions_recorder()->WriteRecordedPositions();
1565
  EnsureSpace ensure_space(this);
1566
  DCHECK(!RelocInfo::IsCodeTarget(rmode));
1567
  EMIT(0xE8);
1568 1569 1570 1571 1572
  if (RelocInfo::IsRuntimeEntry(rmode)) {
    emit(reinterpret_cast<uint32_t>(entry), rmode);
  } else {
    emit(entry - (pc_ + sizeof(int32_t)), rmode);
  }
1573 1574 1575
}


1576 1577 1578 1579 1580 1581
int Assembler::CallSize(const Operand& adr) {
  // Call size is 1 (opcode) + adr.len_ (operand).
  return 1 + adr.len_;
}


1582
void Assembler::call(const Operand& adr) {
1583
  positions_recorder()->WriteRecordedPositions();
1584 1585 1586
  EnsureSpace ensure_space(this);
  EMIT(0xFF);
  emit_operand(edx, adr);
1587 1588 1589 1590 1591
}


int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
  return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1592 1593 1594
}


1595 1596
void Assembler::call(Handle<Code> code,
                     RelocInfo::Mode rmode,
1597
                     TypeFeedbackId ast_id) {
1598
  positions_recorder()->WriteRecordedPositions();
1599
  EnsureSpace ensure_space(this);
1600
  DCHECK(RelocInfo::IsCodeTarget(rmode)
1601
      || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1602
  EMIT(0xE8);
1603
  emit(code, rmode, ast_id);
1604 1605 1606
}


1607
void Assembler::jmp(Label* L, Label::Distance distance) {
1608 1609 1610 1611 1612
  EnsureSpace ensure_space(this);
  if (L->is_bound()) {
    const int short_size = 2;
    const int long_size  = 5;
    int offs = L->pos() - pc_offset();
1613
    DCHECK(offs <= 0);
1614
    if (is_int8(offs - short_size)) {
1615
      // 1110 1011 #8-bit disp.
1616 1617 1618
      EMIT(0xEB);
      EMIT((offs - short_size) & 0xFF);
    } else {
1619
      // 1110 1001 #32-bit disp.
1620 1621 1622
      EMIT(0xE9);
      emit(offs - long_size);
    }
1623 1624 1625
  } else if (distance == Label::kNear) {
    EMIT(0xEB);
    emit_near_disp(L);
1626
  } else {
1627
    // 1110 1001 #32-bit disp.
1628 1629 1630 1631 1632 1633
    EMIT(0xE9);
    emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
  }
}


1634
void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1635
  EnsureSpace ensure_space(this);
1636
  DCHECK(!RelocInfo::IsCodeTarget(rmode));
1637
  EMIT(0xE9);
1638 1639 1640 1641 1642
  if (RelocInfo::IsRuntimeEntry(rmode)) {
    emit(reinterpret_cast<uint32_t>(entry), rmode);
  } else {
    emit(entry - (pc_ + sizeof(int32_t)), rmode);
  }
1643 1644 1645 1646 1647 1648 1649 1650 1651 1652
}


void Assembler::jmp(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xFF);
  emit_operand(esp, adr);
}


1653
void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1654
  EnsureSpace ensure_space(this);
1655
  DCHECK(RelocInfo::IsCodeTarget(rmode));
1656
  EMIT(0xE9);
1657
  emit(code, rmode);
1658 1659 1660
}


1661
void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1662
  EnsureSpace ensure_space(this);
1663
  DCHECK(0 <= cc && static_cast<int>(cc) < 16);
1664 1665 1666 1667
  if (L->is_bound()) {
    const int short_size = 2;
    const int long_size  = 6;
    int offs = L->pos() - pc_offset();
1668
    DCHECK(offs <= 0);
1669 1670 1671 1672 1673 1674 1675 1676 1677 1678
    if (is_int8(offs - short_size)) {
      // 0111 tttn #8-bit disp
      EMIT(0x70 | cc);
      EMIT((offs - short_size) & 0xFF);
    } else {
      // 0000 1111 1000 tttn #32-bit disp
      EMIT(0x0F);
      EMIT(0x80 | cc);
      emit(offs - long_size);
    }
1679 1680 1681
  } else if (distance == Label::kNear) {
    EMIT(0x70 | cc);
    emit_near_disp(L);
1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692
  } else {
    // 0000 1111 1000 tttn #32-bit disp
    // Note: could eliminate cond. jumps to this jump if condition
    //       is the same however, seems to be rather unlikely case.
    EMIT(0x0F);
    EMIT(0x80 | cc);
    emit_disp(L, Displacement::OTHER);
  }
}


1693
void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1694
  EnsureSpace ensure_space(this);
1695
  DCHECK((0 <= cc) && (static_cast<int>(cc) < 16));
1696
  // 0000 1111 1000 tttn #32-bit disp.
1697 1698
  EMIT(0x0F);
  EMIT(0x80 | cc);
1699 1700 1701 1702 1703
  if (RelocInfo::IsRuntimeEntry(rmode)) {
    emit(reinterpret_cast<uint32_t>(entry), rmode);
  } else {
    emit(entry - (pc_ + sizeof(int32_t)), rmode);
  }
1704 1705 1706
}


1707
void Assembler::j(Condition cc, Handle<Code> code, RelocInfo::Mode rmode) {
1708 1709 1710 1711
  EnsureSpace ensure_space(this);
  // 0000 1111 1000 tttn #32-bit disp
  EMIT(0x0F);
  EMIT(0x80 | cc);
1712
  emit(code, rmode);
1713 1714 1715
}


1716
// FPU instructions.
1717 1718 1719 1720 1721 1722 1723

void Assembler::fld(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xD9, 0xC0, i);
}


1724 1725 1726 1727 1728 1729
void Assembler::fstp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDD, 0xD8, i);
}


1730 1731 1732 1733 1734 1735 1736
void Assembler::fld1() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xE8);
}


1737 1738 1739 1740 1741 1742 1743
void Assembler::fldpi() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xEB);
}


1744 1745 1746 1747 1748 1749 1750
void Assembler::fldz() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xEE);
}


1751 1752 1753 1754 1755 1756 1757
void Assembler::fldln2() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xED);
}


1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778
void Assembler::fld_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  emit_operand(eax, adr);
}


void Assembler::fld_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDD);
  emit_operand(eax, adr);
}


void Assembler::fstp_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  emit_operand(ebx, adr);
}


1779 1780 1781 1782 1783 1784 1785
void Assembler::fst_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  emit_operand(edx, adr);
}


1786 1787 1788 1789 1790 1791 1792
void Assembler::fstp_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDD);
  emit_operand(ebx, adr);
}


1793 1794 1795 1796 1797 1798 1799
void Assembler::fst_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDD);
  emit_operand(edx, adr);
}


1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820
void Assembler::fild_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDB);
  emit_operand(eax, adr);
}


void Assembler::fild_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDF);
  emit_operand(ebp, adr);
}


void Assembler::fistp_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDB);
  emit_operand(ebx, adr);
}


1821
void Assembler::fisttp_s(const Operand& adr) {
1822
  DCHECK(IsEnabled(SSE3));
1823 1824 1825 1826 1827 1828
  EnsureSpace ensure_space(this);
  EMIT(0xDB);
  emit_operand(ecx, adr);
}


1829
void Assembler::fisttp_d(const Operand& adr) {
1830
  DCHECK(IsEnabled(SSE3));
1831 1832 1833 1834 1835 1836
  EnsureSpace ensure_space(this);
  EMIT(0xDD);
  emit_operand(ecx, adr);
}


1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864
void Assembler::fist_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDB);
  emit_operand(edx, adr);
}


void Assembler::fistp_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDF);
  emit_operand(edi, adr);
}


void Assembler::fabs() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xE1);
}


void Assembler::fchs() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xE0);
}


1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878
void Assembler::fcos() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xFF);
}


void Assembler::fsin() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xFE);
}


1879 1880 1881 1882 1883 1884 1885
void Assembler::fptan() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xF2);
}


1886 1887 1888 1889 1890 1891 1892
void Assembler::fyl2x() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xF1);
}


1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913
void Assembler::f2xm1() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xF0);
}


void Assembler::fscale() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xFD);
}


void Assembler::fninit() {
  EnsureSpace ensure_space(this);
  EMIT(0xDB);
  EMIT(0xE3);
}


1914 1915 1916 1917 1918 1919
void Assembler::fadd(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDC, 0xC0, i);
}


1920 1921 1922 1923 1924 1925
void Assembler::fadd_i(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xD8, 0xC0, i);
}


1926 1927 1928 1929 1930 1931
void Assembler::fsub(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDC, 0xE8, i);
}


1932 1933 1934 1935 1936 1937
void Assembler::fsub_i(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xD8, 0xE0, i);
}


1938 1939 1940 1941 1942 1943 1944
void Assembler::fisub_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
  EMIT(0xDA);
  emit_operand(esp, adr);
}


1945 1946 1947 1948 1949 1950
void Assembler::fmul_i(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xD8, 0xC8, i);
}


1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962
void Assembler::fmul(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDC, 0xC8, i);
}


void Assembler::fdiv(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDC, 0xF8, i);
}


1963 1964 1965 1966 1967 1968
void Assembler::fdiv_i(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xD8, 0xF0, i);
}


1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051
void Assembler::faddp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xC0, i);
}


void Assembler::fsubp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xE8, i);
}


void Assembler::fsubrp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xE0, i);
}


void Assembler::fmulp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xC8, i);
}


void Assembler::fdivp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xF8, i);
}


void Assembler::fprem() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xF8);
}


void Assembler::fprem1() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xF5);
}


void Assembler::fxch(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xD9, 0xC8, i);
}


void Assembler::fincstp() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xF7);
}


void Assembler::ffree(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDD, 0xC0, i);
}


void Assembler::ftst() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xE4);
}


void Assembler::fucomp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDD, 0xE8, i);
}


void Assembler::fucompp() {
  EnsureSpace ensure_space(this);
  EMIT(0xDA);
  EMIT(0xE9);
}


2052 2053 2054 2055 2056 2057 2058
void Assembler::fucomi(int i) {
  EnsureSpace ensure_space(this);
  EMIT(0xDB);
  EMIT(0xE8 + i);
}


2059 2060 2061 2062 2063 2064 2065
void Assembler::fucomip() {
  EnsureSpace ensure_space(this);
  EMIT(0xDF);
  EMIT(0xE9);
}


2066 2067 2068 2069 2070 2071 2072 2073 2074
void Assembler::fcompp() {
  EnsureSpace ensure_space(this);
  EMIT(0xDE);
  EMIT(0xD9);
}


void Assembler::fnstsw_ax() {
  EnsureSpace ensure_space(this);
2075
  EMIT(0xDF);
2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092
  EMIT(0xE0);
}


void Assembler::fwait() {
  EnsureSpace ensure_space(this);
  EMIT(0x9B);
}


void Assembler::frndint() {
  EnsureSpace ensure_space(this);
  EMIT(0xD9);
  EMIT(0xFC);
}


2093 2094 2095 2096 2097 2098 2099
void Assembler::fnclex() {
  EnsureSpace ensure_space(this);
  EMIT(0xDB);
  EMIT(0xE2);
}


2100 2101 2102 2103 2104 2105
void Assembler::sahf() {
  EnsureSpace ensure_space(this);
  EMIT(0x9E);
}


2106
void Assembler::setcc(Condition cc, Register reg) {
2107
  DCHECK(reg.is_byte_register());
2108 2109 2110 2111 2112 2113 2114
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x90 | cc);
  EMIT(0xC0 | reg.code());
}


2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132
void Assembler::cvttss2si(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x2C);
  emit_operand(dst, src);
}


void Assembler::cvttsd2si(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x2C);
  emit_operand(dst, src);
}


2133 2134 2135 2136 2137 2138 2139 2140 2141
void Assembler::cvtsd2si(Register dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x2D);
  emit_sse_operand(dst, src);
}


2142 2143 2144 2145 2146 2147 2148 2149 2150
void Assembler::cvtsi2ss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x2A);
  emit_sse_operand(dst, src);
}


2151 2152 2153 2154 2155 2156 2157 2158 2159
void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x2A);
  emit_sse_operand(dst, src);
}


2160
void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
2161 2162 2163 2164 2165 2166 2167 2168
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x5A);
  emit_sse_operand(dst, src);
}


2169
void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
2170 2171 2172 2173 2174 2175 2176 2177
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x5A);
  emit_sse_operand(dst, src);
}


2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195
void Assembler::addsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x58);
  emit_sse_operand(dst, src);
}


void Assembler::mulsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x59);
  emit_sse_operand(dst, src);
}


2196 2197 2198 2199 2200 2201 2202 2203 2204
void Assembler::subsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x5C);
  emit_sse_operand(dst, src);
}


2205
void Assembler::divsd(XMMRegister dst, const Operand& src) {
2206 2207 2208 2209 2210 2211 2212 2213
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x5E);
  emit_sse_operand(dst, src);
}


2214 2215 2216 2217 2218 2219 2220 2221 2222
void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x57);
  emit_sse_operand(dst, src);
}


2223
void Assembler::andps(XMMRegister dst, const Operand& src) {
2224 2225 2226 2227 2228 2229 2230
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x54);
  emit_sse_operand(dst, src);
}


2231
void Assembler::orps(XMMRegister dst, const Operand& src) {
2232 2233 2234 2235 2236 2237 2238
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x56);
  emit_sse_operand(dst, src);
}


2239
void Assembler::xorps(XMMRegister dst, const Operand& src) {
2240 2241 2242 2243 2244 2245 2246
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x57);
  emit_sse_operand(dst, src);
}


2247
void Assembler::addps(XMMRegister dst, const Operand& src) {
2248 2249
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
2250
  EMIT(0x58);
2251 2252 2253 2254
  emit_sse_operand(dst, src);
}


2255
void Assembler::subps(XMMRegister dst, const Operand& src) {
2256 2257
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
2258
  EMIT(0x5C);
2259 2260 2261 2262
  emit_sse_operand(dst, src);
}


2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278
void Assembler::mulps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x59);
  emit_sse_operand(dst, src);
}


void Assembler::divps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x5E);
  emit_sse_operand(dst, src);
}


2279 2280 2281 2282 2283 2284 2285 2286 2287
void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x51);
  emit_sse_operand(dst, src);
}


2288
void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2289 2290 2291
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
2292
  EMIT(0x54);
2293 2294 2295 2296
  emit_sse_operand(dst, src);
}


2297
void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2298 2299 2300
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
2301
  EMIT(0x56);
2302 2303 2304 2305
  emit_sse_operand(dst, src);
}


2306 2307 2308 2309 2310 2311 2312 2313 2314
void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x2E);
  emit_sse_operand(dst, src);
}


2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327
void Assembler::roundss(XMMRegister dst, XMMRegister src, RoundingMode mode) {
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x3A);
  EMIT(0x0A);
  emit_sse_operand(dst, src);
  // Mask precision exeption.
  EMIT(static_cast<byte>(mode) | 0x8);
}


2328
void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
2329
  DCHECK(IsEnabled(SSE4_1));
2330 2331 2332 2333 2334 2335 2336 2337 2338 2339
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x3A);
  EMIT(0x0B);
  emit_sse_operand(dst, src);
  // Mask precision exeption.
  EMIT(static_cast<byte>(mode) | 0x8);
}

2340

2341 2342 2343 2344 2345 2346 2347 2348 2349
void Assembler::movmskpd(Register dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x50);
  emit_sse_operand(dst, src);
}


2350 2351 2352 2353 2354 2355 2356 2357
void Assembler::movmskps(Register dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x50);
  emit_sse_operand(dst, src);
}


2358 2359 2360 2361 2362 2363 2364 2365 2366
void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x76);
  emit_sse_operand(dst, src);
}


2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384
void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x62);
  emit_sse_operand(dst, src);
}


void Assembler::punpckhdq(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x6A);
  emit_sse_operand(dst, src);
}


2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402
void Assembler::maxsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x5F);
  emit_sse_operand(dst, src);
}


void Assembler::minsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0x5D);
  emit_sse_operand(dst, src);
}


2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420
void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);
  EMIT(0x0F);
  EMIT(0xC2);
  emit_sse_operand(dst, src);
  EMIT(1);  // LT == 1
}


void Assembler::movaps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x28);
  emit_sse_operand(dst, src);
}


2421
void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2422
  DCHECK(is_uint8(imm8));
2423 2424 2425 2426 2427 2428 2429 2430
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0xC6);
  emit_sse_operand(dst, src);
  EMIT(imm8);
}


2431
void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x7F);
  emit_sse_operand(src, dst);
}


void Assembler::movdqa(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x6F);
  emit_sse_operand(dst, src);
}


void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x7F);
  emit_sse_operand(src, dst);
}


void Assembler::movdqu(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x6F);
  emit_sse_operand(dst, src);
}


2467
void Assembler::prefetch(const Operand& src, int level) {
2468
  DCHECK(is_uint2(level));
2469 2470 2471
  EnsureSpace ensure_space(this);
  EMIT(0x0F);
  EMIT(0x18);
2472 2473
  // Emit hint number in Reg position of RegR/M.
  XMMRegister code = XMMRegister::from_code(level);
2474 2475 2476 2477
  emit_sse_operand(code, src);
}


2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494
void Assembler::movsd(const Operand& dst, XMMRegister src ) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);  // double
  EMIT(0x0F);
  EMIT(0x11);  // store
  emit_sse_operand(src, dst);
}


void Assembler::movsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF2);  // double
  EMIT(0x0F);
  EMIT(0x10);  // load
  emit_sse_operand(dst, src);
}

2495

2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513
void Assembler::movss(const Operand& dst, XMMRegister src ) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);  // float
  EMIT(0x0F);
  EMIT(0x11);  // store
  emit_sse_operand(src, dst);
}


void Assembler::movss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);  // float
  EMIT(0x0F);
  EMIT(0x10);  // load
  emit_sse_operand(dst, src);
}


2514 2515 2516 2517 2518 2519 2520 2521 2522
void Assembler::movd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x6E);
  emit_sse_operand(dst, src);
}


2523 2524 2525 2526 2527 2528 2529 2530 2531
void Assembler::movd(const Operand& dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x7E);
  emit_sse_operand(src, dst);
}


2532
void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2533 2534
  DCHECK(IsEnabled(SSE4_1));
  DCHECK(is_uint8(imm8));
2535 2536 2537 2538 2539
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x3A);
  EMIT(0x17);
2540
  emit_sse_operand(src, dst);
2541 2542 2543 2544
  EMIT(imm8);
}


2545 2546 2547 2548 2549 2550 2551 2552 2553
void Assembler::pand(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0xDB);
  emit_sse_operand(dst, src);
}


2554 2555 2556 2557 2558 2559 2560 2561 2562
void Assembler::pxor(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0xEF);
  emit_sse_operand(dst, src);
}


2563 2564 2565 2566 2567 2568 2569 2570 2571
void Assembler::por(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0xEB);
  emit_sse_operand(dst, src);
}


2572
void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2573
  DCHECK(IsEnabled(SSE4_1));
2574 2575 2576 2577 2578 2579 2580 2581
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x38);
  EMIT(0x17);
  emit_sse_operand(dst, src);
}

2582

2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602
void Assembler::pslld(XMMRegister reg, int8_t shift) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x72);
  emit_sse_operand(esi, reg);  // esi == 6
  EMIT(shift);
}


void Assembler::psrld(XMMRegister reg, int8_t shift) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x72);
  emit_sse_operand(edx, reg);  // edx == 2
  EMIT(shift);
}


2603
void Assembler::psllq(XMMRegister reg, int8_t shift) {
2604 2605 2606 2607 2608
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x73);
  emit_sse_operand(esi, reg);  // esi == 6
2609 2610 2611 2612
  EMIT(shift);
}


2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640
void Assembler::psllq(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0xF3);
  emit_sse_operand(dst, src);
}


void Assembler::psrlq(XMMRegister reg, int8_t shift) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x73);
  emit_sse_operand(edx, reg);  // edx == 2
  EMIT(shift);
}


void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0xD3);
  emit_sse_operand(dst, src);
}


2641
void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
2642 2643 2644 2645 2646 2647 2648 2649 2650 2651
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x70);
  emit_sse_operand(dst, src);
  EMIT(shuffle);
}


void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2652
  DCHECK(IsEnabled(SSE4_1));
2653 2654 2655 2656 2657 2658 2659
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x3A);
  EMIT(0x16);
  emit_sse_operand(src, dst);
  EMIT(offset);
2660 2661 2662 2663
}


void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2664
  DCHECK(IsEnabled(SSE4_1));
2665 2666 2667 2668 2669 2670 2671
  EnsureSpace ensure_space(this);
  EMIT(0x66);
  EMIT(0x0F);
  EMIT(0x3A);
  EMIT(0x22);
  emit_sse_operand(dst, src);
  EMIT(offset);
2672 2673 2674
}


2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710
void Assembler::addss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x58);
  emit_sse_operand(dst, src);
}


void Assembler::subss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x5C);
  emit_sse_operand(dst, src);
}


void Assembler::mulss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x59);
  emit_sse_operand(dst, src);
}


void Assembler::divss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x5E);
  emit_sse_operand(dst, src);
}


2711 2712 2713 2714 2715 2716 2717 2718 2719
void Assembler::sqrtss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x51);
  emit_sse_operand(dst, src);
}


2720 2721 2722 2723 2724 2725 2726 2727
void Assembler::ucomiss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0x0f);
  EMIT(0x2e);
  emit_sse_operand(dst, src);
}


2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745
void Assembler::maxss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x5F);
  emit_sse_operand(dst, src);
}


void Assembler::minss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0x5D);
  emit_sse_operand(dst, src);
}


2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766
// AVX instructions
void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
                       const Operand& src2) {
  DCHECK(IsEnabled(FMA3));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(src1, kLIG, k66, k0F38, kW1);
  EMIT(op);
  emit_sse_operand(dst, src2);
}


void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
                       const Operand& src2) {
  DCHECK(IsEnabled(FMA3));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(src1, kLIG, k66, k0F38, kW0);
  EMIT(op);
  emit_sse_operand(dst, src2);
}


2767 2768 2769 2770 2771 2772 2773 2774 2775 2776
void Assembler::vsd(byte op, XMMRegister dst, XMMRegister src1,
                    const Operand& src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(src1, kLIG, kF2, k0F, kWIG);
  EMIT(op);
  emit_sse_operand(dst, src2);
}


2777 2778 2779 2780 2781 2782 2783 2784 2785 2786
void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1,
                    const Operand& src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(src1, kLIG, kF3, k0F, kWIG);
  EMIT(op);
  emit_sse_operand(dst, src2);
}


2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806
void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1,
                    const Operand& src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(src1, kL128, kNone, k0F, kWIG);
  EMIT(op);
  emit_sse_operand(dst, src2);
}


void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1,
                    const Operand& src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(src1, kL128, k66, k0F, kWIG);
  EMIT(op);
  emit_sse_operand(dst, src2);
}


2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867
void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(vreg, kLZ, kNone, k0F38, kW0);
  EMIT(op);
  emit_operand(reg, rm);
}


void Assembler::tzcnt(Register dst, const Operand& src) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0xBC);
  emit_operand(dst, src);
}


void Assembler::lzcnt(Register dst, const Operand& src) {
  DCHECK(IsEnabled(LZCNT));
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0xBD);
  emit_operand(dst, src);
}


void Assembler::popcnt(Register dst, const Operand& src) {
  DCHECK(IsEnabled(POPCNT));
  EnsureSpace ensure_space(this);
  EMIT(0xF3);
  EMIT(0x0F);
  EMIT(0xB8);
  emit_operand(dst, src);
}


void Assembler::bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg,
                     const Operand& rm) {
  DCHECK(IsEnabled(BMI2));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(vreg, kLZ, pp, k0F38, kW0);
  EMIT(op);
  emit_operand(reg, rm);
}


void Assembler::rorx(Register dst, const Operand& src, byte imm8) {
  DCHECK(IsEnabled(BMI2));
  DCHECK(is_uint8(imm8));
  Register vreg = {0};  // VEX.vvvv unused
  EnsureSpace ensure_space(this);
  emit_vex_prefix(vreg, kLZ, kF2, k0F3A, kW0);
  EMIT(0xF0);
  emit_operand(dst, src);
  EMIT(imm8);
}


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void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
  Register ireg = { reg.code() };
  emit_operand(ireg, adr);
}


void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
  EMIT(0xC0 | dst.code() << 3 | src.code());
}


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void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
  EMIT(0xC0 | dst.code() << 3 | src.code());
}


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void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
  EMIT(0xC0 | (dst.code() << 3) | src.code());
}


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void Assembler::emit_vex_prefix(XMMRegister vreg, VectorLength l, SIMDPrefix pp,
                                LeadingOpcode mm, VexW w) {
  if (mm != k0F || w != kW0) {
    EMIT(0xc4);
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    // Change RXB from "110" to "111" to align with gdb disassembler.
    EMIT(0xe0 | mm);
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    EMIT(w | ((~vreg.code() & 0xf) << 3) | l | pp);
  } else {
    EMIT(0xc5);
    EMIT(((~vreg.code()) << 3) | l | pp);
  }
}


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void Assembler::emit_vex_prefix(Register vreg, VectorLength l, SIMDPrefix pp,
                                LeadingOpcode mm, VexW w) {
  XMMRegister ivreg = {vreg.code()};
  emit_vex_prefix(ivreg, l, pp, mm, w);
}


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void Assembler::GrowBuffer() {
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  DCHECK(buffer_overflow());
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  if (!own_buffer_) FATAL("external code buffer is too small");

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  // Compute new buffer size.
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  CodeDesc desc;  // the new buffer
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  desc.buffer_size = 2 * buffer_size_;

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  // Some internal data structures overflow for very large buffers,
  // they must ensure that kMaximalBufferSize is not too large.
  if ((desc.buffer_size > kMaximalBufferSize) ||
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      (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
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    V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
  }

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  // Set up new buffer.
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  desc.buffer = NewArray<byte>(desc.buffer_size);
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  desc.origin = this;
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  desc.instr_size = pc_offset();
  desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());

  // Clear the buffer in debug mode. Use 'int3' instructions to make
  // sure to get into problems if we ever run uninitialized code.
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#ifdef DEBUG
  memset(desc.buffer, 0xCC, desc.buffer_size);
#endif
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  // Copy the data.
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  int pc_delta = desc.buffer - buffer_;
  int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
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  MemMove(desc.buffer, buffer_, desc.instr_size);
  MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
          desc.reloc_size);
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  // Switch buffers.
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  DeleteArray(buffer_);
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  buffer_ = desc.buffer;
  buffer_size_ = desc.buffer_size;
  pc_ += pc_delta;
  reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
                               reloc_info_writer.last_pc() + pc_delta);

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  // Relocate internal references.
  for (auto pos : internal_reference_positions_) {
    int32_t* p = reinterpret_cast<int32_t*>(buffer_ + pos);
    *p += pc_delta;
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  }

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  DCHECK(!buffer_overflow());
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}


void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
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  DCHECK(is_uint8(op1) && is_uint8(op2));  // wrong opcode
  DCHECK(is_uint8(imm8));
  DCHECK((op1 & 0x01) == 0);  // should be 8bit operation
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  EMIT(op1);
  EMIT(op2 | dst.code());
  EMIT(imm8);
}


void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
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  DCHECK((0 <= sel) && (sel <= 7));
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  Register ireg = { sel };
  if (x.is_int8()) {
    EMIT(0x83);  // using a sign-extended 8-bit immediate.
    emit_operand(ireg, dst);
    EMIT(x.x_ & 0xFF);
  } else if (dst.is_reg(eax)) {
    EMIT((sel << 3) | 0x05);  // short form if the destination is eax.
    emit(x);
  } else {
    EMIT(0x81);  // using a literal 32-bit immediate.
    emit_operand(ireg, dst);
    emit(x);
  }
}


void Assembler::emit_operand(Register reg, const Operand& adr) {
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  const unsigned length = adr.len_;
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  DCHECK(length > 0);
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  // Emit updated ModRM byte containing the given register.
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  pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
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  // Emit the rest of the encoded operand.
  for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
  pc_ += length;

  // Emit relocation information if necessary.
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  if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
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    pc_ -= sizeof(int32_t);  // pc_ must be *at* disp32
    RecordRelocInfo(adr.rmode_);
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    if (adr.rmode_ == RelocInfo::INTERNAL_REFERENCE) {  // Fixup for labels
      emit_label(*reinterpret_cast<Label**>(pc_));
    } else {
      pc_ += sizeof(int32_t);
    }
  }
}


void Assembler::emit_label(Label* label) {
  if (label->is_bound()) {
    internal_reference_positions_.push_back(pc_offset());
    emit(reinterpret_cast<uint32_t>(buffer_ + label->pos()));
  } else {
    emit_disp(label, Displacement::CODE_ABSOLUTE);
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  }
}


void Assembler::emit_farith(int b1, int b2, int i) {
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  DCHECK(is_uint8(b1) && is_uint8(b2));  // wrong opcode
  DCHECK(0 <= i &&  i < 8);  // illegal stack offset
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  EMIT(b1);
  EMIT(b2 + i);
}

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void Assembler::db(uint8_t data) {
  EnsureSpace ensure_space(this);
  EMIT(data);
}


void Assembler::dd(uint32_t data) {
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  EnsureSpace ensure_space(this);
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  emit(data);
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}

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void Assembler::dq(uint64_t data) {
  EnsureSpace ensure_space(this);
  emit_q(data);
}


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void Assembler::dd(Label* label) {
  EnsureSpace ensure_space(this);
  RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
  emit_label(label);
}


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void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
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  DCHECK(!RelocInfo::IsNone(rmode));
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  // Don't record external references unless the heap will be serialized.
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  if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
      !serializer_enabled() && !emit_debug_code()) {
    return;
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  }
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  RelocInfo rinfo(isolate(), pc_, rmode, data, NULL);
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  reloc_info_writer.Write(&rinfo);
}

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#ifdef GENERATED_CODE_COVERAGE
static FILE* coverage_log = NULL;


static void InitCoverageLog() {
  char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
  if (file_name != NULL) {
    coverage_log = fopen(file_name, "aw+");
  }
}


void LogGeneratedCodeCoverage(const char* file_line) {
  const char* return_address = (&file_line)[-1];
  char* push_insn = const_cast<char*>(return_address - 12);
  push_insn[0] = 0xeb;  // Relative branch insn.
  push_insn[1] = 13;    // Skip over coverage insns.
  if (coverage_log != NULL) {
    fprintf(coverage_log, "%s\n", file_line);
    fflush(coverage_log);
  }
}

#endif

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}  // namespace internal
}  // namespace v8
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#endif  // V8_TARGET_ARCH_IA32