assembler-arm-inl.h 16.4 KB
Newer Older
1 2 3
// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
4
// Redistribution and use in source and binary forms, with or without
5 6 7 8 9 10 11 12 13 14
// modification, are permitted provided that the following conditions
// are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
15
//
16 17 18
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
19 20 21
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 23 24 25 26 27 28 29 30 31 32 33 34
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
// OF THE POSSIBILITY OF SUCH DAMAGE.

// The original source code covered by the above license above has been modified
// significantly by Google Inc.
35
// Copyright 2012 the V8 project authors. All rights reserved.
36

37 38
#ifndef V8_ARM_ASSEMBLER_ARM_INL_H_
#define V8_ARM_ASSEMBLER_ARM_INL_H_
39

40
#include "src/arm/assembler-arm.h"
41

42
#include "src/assembler.h"
43
#include "src/debug/debug.h"
44
#include "src/objects-inl.h"
45
#include "src/objects/smi.h"
46

47 48
namespace v8 {
namespace internal {
49

50
bool CpuFeatures::SupportsOptimizer() { return true; }
51

52
bool CpuFeatures::SupportsWasmSimd128() { return IsSupported(NEON); }
53

54
int DoubleRegister::NumRegisters() {
55
  return CpuFeatures::IsSupported(VFP32DREGS) ? 32 : 16;
56 57 58
}


59
void RelocInfo::apply(intptr_t delta) {
60
  if (RelocInfo::IsInternalReference(rmode_)) {
61 62 63
    // absolute code pointer inside code object moves with the code object.
    int32_t* p = reinterpret_cast<int32_t*>(pc_);
    *p += delta;  // relocate entry
64 65 66 67
  } else if (RelocInfo::IsRelativeCodeTarget(rmode_)) {
    Instruction* branch = Instruction::At(pc_);
    int32_t branch_offset = branch->GetBranchOffset() + delta;
    branch->SetBranchOffset(branch_offset);
68
  }
69 70 71 72
}


Address RelocInfo::target_address() {
73 74
  DCHECK(IsCodeTargetMode(rmode_) || IsRuntimeEntry(rmode_) ||
         IsWasmCall(rmode_));
75
  return Assembler::target_address_at(pc_, constant_pool_);
76 77
}

78
Address RelocInfo::target_address_address() {
79
  DCHECK(HasTargetAddressAddress());
80
  if (Assembler::IsMovW(Memory<int32_t>(pc_))) {
81
    return pc_;
82
  } else {
83
    DCHECK(Assembler::IsLdrPcImmediateOffset(Memory<int32_t>(pc_)));
84
    return constant_pool_entry_address();
85
  }
86 87 88
}


89
Address RelocInfo::constant_pool_entry_address() {
90
  DCHECK(IsInConstantPool());
91
  return Assembler::constant_pool_entry_address(pc_, constant_pool_);
92 93 94
}


95
int RelocInfo::target_address_size() {
96
  return kPointerSize;
97 98
}

99
HeapObject* RelocInfo::target_object() {
100
  DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
101 102
  return HeapObject::cast(reinterpret_cast<Object*>(
      Assembler::target_address_at(pc_, constant_pool_)));
103 104
}

105
Handle<HeapObject> RelocInfo::target_object_handle(Assembler* origin) {
106
  if (IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT) {
107
    return Handle<HeapObject>(reinterpret_cast<Address*>(
108 109 110 111
        Assembler::target_address_at(pc_, constant_pool_)));
  }
  DCHECK(IsRelativeCodeTarget(rmode_));
  return origin->relative_code_target_object_handle_at(pc_);
112 113
}

114
void RelocInfo::set_target_object(Heap* heap, HeapObject* target,
115 116
                                  WriteBarrierMode write_barrier_mode,
                                  ICacheFlushMode icache_flush_mode) {
117
  DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
118
  Assembler::set_target_address_at(pc_, constant_pool_,
119 120
                                   reinterpret_cast<Address>(target),
                                   icache_flush_mode);
121
  if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != nullptr) {
122
    WriteBarrierForCode(host(), this, target);
123
  }
124 125 126
}


127
Address RelocInfo::target_external_reference() {
128
  DCHECK(rmode_ == EXTERNAL_REFERENCE);
129
  return Assembler::target_address_at(pc_, constant_pool_);
130 131
}

132 133 134 135 136 137
void RelocInfo::set_target_external_reference(
    Address target, ICacheFlushMode icache_flush_mode) {
  DCHECK(rmode_ == RelocInfo::EXTERNAL_REFERENCE);
  Assembler::set_target_address_at(pc_, constant_pool_, target,
                                   icache_flush_mode);
}
138

139 140
Address RelocInfo::target_internal_reference() {
  DCHECK(rmode_ == INTERNAL_REFERENCE);
141
  return Memory<Address>(pc_);
142 143 144
}


145
Address RelocInfo::target_internal_reference_address() {
146
  DCHECK(rmode_ == INTERNAL_REFERENCE);
147
  return pc_;
148 149
}

150
Address RelocInfo::target_runtime_entry(Assembler* origin) {
151
  DCHECK(IsRuntimeEntry(rmode_));
152 153 154
  return target_address();
}

155
void RelocInfo::set_target_runtime_entry(Address target,
156 157
                                         WriteBarrierMode write_barrier_mode,
                                         ICacheFlushMode icache_flush_mode) {
158
  DCHECK(IsRuntimeEntry(rmode_));
159
  if (target_address() != target)
160
    set_target_address(target, write_barrier_mode, icache_flush_mode);
161 162
}

163 164 165 166 167
Address RelocInfo::target_off_heap_target() {
  DCHECK(IsOffHeapTarget(rmode_));
  return Assembler::target_address_at(pc_, constant_pool_);
}

168
void RelocInfo::WipeOut() {
169 170
  DCHECK(IsEmbeddedObject(rmode_) || IsCodeTarget(rmode_) ||
         IsRuntimeEntry(rmode_) || IsExternalReference(rmode_) ||
171
         IsInternalReference(rmode_) || IsOffHeapTarget(rmode_));
172
  if (IsInternalReference(rmode_)) {
173
    Memory<Address>(pc_) = kNullAddress;
174
  } else {
175
    Assembler::set_target_address_at(pc_, constant_pool_, kNullAddress);
176
  }
177 178
}

179 180 181
Handle<Code> Assembler::relative_code_target_object_handle_at(
    Address pc) const {
  Instruction* branch = Instruction::At(pc);
182
  int code_target_index = branch->GetBranchOffset() / kInstrSize;
183 184 185
  return GetCodeTarget(code_target_index);
}

186
template <typename ObjectVisitor>
187
void RelocInfo::Visit(ObjectVisitor* visitor) {
188 189
  RelocInfo::Mode mode = rmode();
  if (mode == RelocInfo::EMBEDDED_OBJECT) {
190
    visitor->VisitEmbeddedPointer(host(), this);
191
  } else if (RelocInfo::IsCodeTargetMode(mode)) {
192
    visitor->VisitCodeTarget(host(), this);
193
  } else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
194
    visitor->VisitExternalReference(host(), this);
195
  } else if (mode == RelocInfo::INTERNAL_REFERENCE) {
196
    visitor->VisitInternalReference(host(), this);
197
  } else if (RelocInfo::IsRuntimeEntry(mode)) {
198
    visitor->VisitRuntimeEntry(host(), this);
199 200
  } else if (RelocInfo::IsOffHeapTarget(mode)) {
    visitor->VisitOffHeapTarget(host(), this);
201 202 203
  }
}

204
Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) : rmode_(rmode) {
205
  value_.immediate = immediate;
206 207
}

208
Operand Operand::Zero() { return Operand(static_cast<int32_t>(0)); }
209

210 211
Operand::Operand(const ExternalReference& f)
    : rmode_(RelocInfo::EXTERNAL_REFERENCE) {
212
  value_.immediate = static_cast<int32_t>(f.address());
213 214
}

215 216
Operand::Operand(Smi value) : rmode_(RelocInfo::NONE) {
  value_.immediate = static_cast<intptr_t>(value.ptr());
217 218
}

219
Operand::Operand(Register rm) : rm_(rm), shift_op_(LSL), shift_imm_(0) {}
220 221 222 223 224

void Assembler::CheckBuffer() {
  if (buffer_space() <= kGap) {
    GrowBuffer();
  }
225
  MaybeCheckConstPool();
226 227 228 229 230 231 232 233 234 235
}


void Assembler::emit(Instr x) {
  CheckBuffer();
  *reinterpret_cast<Instr*>(pc_) = x;
  pc_ += kInstrSize;
}


236 237 238
Address Assembler::target_address_from_return_address(Address pc) {
  // Returns the address of the call target from the return address that will
  // be returned to after a call.
239
  // Call sequence on V7 or later is:
240 241 242 243
  //  movw  ip, #... @ call address low 16
  //  movt  ip, #... @ call address high 16
  //  blx   ip
  //                      @ return address
244 245 246 247 248 249 250 251
  // For V6 when the constant pool is unavailable, it is:
  //  mov  ip, #...     @ call address low 8
  //  orr  ip, ip, #... @ call address 2nd 8
  //  orr  ip, ip, #... @ call address 3rd 8
  //  orr  ip, ip, #... @ call address high 8
  //  blx   ip
  //                      @ return address
  // In cases that need frequent patching, the address is in the
252
  // constant pool.  It could be a small constant pool load:
253
  //  ldr   ip, [pc, #...] @ call address
254 255
  //  blx   ip
  //                      @ return address
256
  Address candidate = pc - 2 * kInstrSize;
257
  Instr candidate_instr(Memory<int32_t>(candidate));
258
  if (IsLdrPcImmediateOffset(candidate_instr)) {
259
    return candidate;
260
  } else {
261
    if (CpuFeatures::IsSupported(ARMv7)) {
262
      candidate -= 1 * kInstrSize;
263 264
      DCHECK(IsMovW(Memory<int32_t>(candidate)) &&
             IsMovT(Memory<int32_t>(candidate + kInstrSize)));
265
    } else {
266
      candidate -= 3 * kInstrSize;
267 268 269 270
      DCHECK(IsMovImmed(Memory<int32_t>(candidate)) &&
             IsOrrImmed(Memory<int32_t>(candidate + kInstrSize)) &&
             IsOrrImmed(Memory<int32_t>(candidate + 2 * kInstrSize)) &&
             IsOrrImmed(Memory<int32_t>(candidate + 3 * kInstrSize)));
271
    }
272
    return candidate;
273 274 275 276 277
  }
}


Address Assembler::return_address_from_call_start(Address pc) {
278
  if (IsLdrPcImmediateOffset(Memory<int32_t>(pc))) {
279
    // Load from constant pool, small section.
280 281
    return pc + kInstrSize * 2;
  } else {
282
    if (CpuFeatures::IsSupported(ARMv7)) {
283 284
      DCHECK(IsMovW(Memory<int32_t>(pc)));
      DCHECK(IsMovT(Memory<int32_t>(pc + kInstrSize)));
285 286
      // A movw / movt load immediate.
      return pc + kInstrSize * 3;
287
    } else {
288 289 290 291
      DCHECK(IsMovImmed(Memory<int32_t>(pc)));
      DCHECK(IsOrrImmed(Memory<int32_t>(pc + kInstrSize)));
      DCHECK(IsOrrImmed(Memory<int32_t>(pc + 2 * kInstrSize)));
      DCHECK(IsOrrImmed(Memory<int32_t>(pc + 3 * kInstrSize)));
292 293
      // A mov / orr load immediate.
      return pc + kInstrSize * 5;
294
    }
295
  }
296 297
}

298
void Assembler::deserialization_set_special_target_at(
299
    Address constant_pool_entry, Code code, Address target) {
300
  Memory<Address>(constant_pool_entry) = target;
301 302
}

303 304 305 306
int Assembler::deserialization_special_target_size(Address location) {
  return kSpecialTargetSize;
}

307
void Assembler::deserialization_set_target_internal_reference_at(
308
    Address pc, Address target, RelocInfo::Mode mode) {
309
  Memory<Address>(pc) = target;
310 311 312
}


313
bool Assembler::is_constant_pool_load(Address pc) {
314
  return IsLdrPcImmediateOffset(Memory<int32_t>(pc));
315 316 317
}


318 319
Address Assembler::constant_pool_entry_address(Address pc,
                                               Address constant_pool) {
320 321
  DCHECK(Assembler::IsLdrPcImmediateOffset(Memory<int32_t>(pc)));
  Instr instr = Memory<int32_t>(pc);
322
  return pc + GetLdrRegisterImmediateOffset(instr) + Instruction::kPcLoadDelta;
323 324 325
}


326
Address Assembler::target_address_at(Address pc, Address constant_pool) {
327
  if (is_constant_pool_load(pc)) {
328
    // This is a constant pool lookup. Return the value in the constant pool.
329 330
    return Memory<Address>(constant_pool_entry_address(pc, constant_pool));
  } else if (CpuFeatures::IsSupported(ARMv7) && IsMovW(Memory<int32_t>(pc))) {
331
    // This is an movw / movt immediate load. Return the immediate.
332 333
    DCHECK(IsMovW(Memory<int32_t>(pc)) &&
           IsMovT(Memory<int32_t>(pc + kInstrSize)));
334 335
    Instruction* movw_instr = Instruction::At(pc);
    Instruction* movt_instr = Instruction::At(pc + kInstrSize);
336 337
    return static_cast<Address>((movt_instr->ImmedMovwMovtValue() << 16) |
                                movw_instr->ImmedMovwMovtValue());
338
  } else if (IsMovImmed(Memory<int32_t>(pc))) {
339
    // This is an mov / orr immediate load. Return the immediate.
340 341 342 343
    DCHECK(IsMovImmed(Memory<int32_t>(pc)) &&
           IsOrrImmed(Memory<int32_t>(pc + kInstrSize)) &&
           IsOrrImmed(Memory<int32_t>(pc + 2 * kInstrSize)) &&
           IsOrrImmed(Memory<int32_t>(pc + 3 * kInstrSize)));
344 345 346 347
    Instr mov_instr = instr_at(pc);
    Instr orr_instr_1 = instr_at(pc + kInstrSize);
    Instr orr_instr_2 = instr_at(pc + 2 * kInstrSize);
    Instr orr_instr_3 = instr_at(pc + 3 * kInstrSize);
348
    Address ret = static_cast<Address>(
349 350 351
        DecodeShiftImm(mov_instr) | DecodeShiftImm(orr_instr_1) |
        DecodeShiftImm(orr_instr_2) | DecodeShiftImm(orr_instr_3));
    return ret;
352 353 354 355
  } else {
    Instruction* branch = Instruction::At(pc);
    int32_t delta = branch->GetBranchOffset();
    return pc + delta + Instruction::kPcLoadDelta;
356 357 358
  }
}

359 360
void Assembler::set_target_address_at(Address pc, Address constant_pool,
                                      Address target,
361
                                      ICacheFlushMode icache_flush_mode) {
362
  if (is_constant_pool_load(pc)) {
363
    // This is a constant pool lookup. Update the entry in the constant pool.
364
    Memory<Address>(constant_pool_entry_address(pc, constant_pool)) = target;
365 366
    // Intuitively, we would think it is necessary to always flush the
    // instruction cache after patching a target address in the code as follows:
367
    //   Assembler::FlushICache(pc, sizeof(target));
368 369 370 371 372
    // However, on ARM, no instruction is actually patched in the case
    // of embedded constants of the form:
    // ldr   ip, [pp, #...]
    // since the instruction accessing this address in the constant pool remains
    // unchanged.
373
  } else if (CpuFeatures::IsSupported(ARMv7) && IsMovW(Memory<int32_t>(pc))) {
374 375
    // This is an movw / movt immediate load. Patch the immediate embedded in
    // the instructions.
376 377
    DCHECK(IsMovW(Memory<int32_t>(pc)));
    DCHECK(IsMovT(Memory<int32_t>(pc + kInstrSize)));
378
    uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc);
379
    uint32_t immediate = static_cast<uint32_t>(target);
380 381
    instr_ptr[0] = PatchMovwImmediate(instr_ptr[0], immediate & 0xFFFF);
    instr_ptr[1] = PatchMovwImmediate(instr_ptr[1], immediate >> 16);
382 383
    DCHECK(IsMovW(Memory<int32_t>(pc)));
    DCHECK(IsMovT(Memory<int32_t>(pc + kInstrSize)));
384
    if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
385
      Assembler::FlushICache(pc, 2 * kInstrSize);
386
    }
387
  } else if (IsMovImmed(Memory<int32_t>(pc))) {
388 389
    // This is an mov / orr immediate load. Patch the immediate embedded in
    // the instructions.
390 391 392 393
    DCHECK(IsMovImmed(Memory<int32_t>(pc)) &&
           IsOrrImmed(Memory<int32_t>(pc + kInstrSize)) &&
           IsOrrImmed(Memory<int32_t>(pc + 2 * kInstrSize)) &&
           IsOrrImmed(Memory<int32_t>(pc + 3 * kInstrSize)));
394
    uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc);
Eric Holk's avatar
Eric Holk committed
395
    uint32_t immediate = static_cast<uint32_t>(target);
396 397 398 399
    instr_ptr[0] = PatchShiftImm(instr_ptr[0], immediate & kImm8Mask);
    instr_ptr[1] = PatchShiftImm(instr_ptr[1], immediate & (kImm8Mask << 8));
    instr_ptr[2] = PatchShiftImm(instr_ptr[2], immediate & (kImm8Mask << 16));
    instr_ptr[3] = PatchShiftImm(instr_ptr[3], immediate & (kImm8Mask << 24));
400 401 402 403
    DCHECK(IsMovImmed(Memory<int32_t>(pc)) &&
           IsOrrImmed(Memory<int32_t>(pc + kInstrSize)) &&
           IsOrrImmed(Memory<int32_t>(pc + 2 * kInstrSize)) &&
           IsOrrImmed(Memory<int32_t>(pc + 3 * kInstrSize)));
404
    if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
405
      Assembler::FlushICache(pc, 4 * kInstrSize);
406
    }
407 408 409 410 411 412 413
  } else {
    intptr_t branch_offset = target - pc - Instruction::kPcLoadDelta;
    Instruction* branch = Instruction::At(pc);
    branch->SetBranchOffset(branch_offset);
    if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
      Assembler::FlushICache(pc, kInstrSize);
    }
414 415 416
  }
}

417 418
EnsureSpace::EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); }

419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447
template <typename T>
bool UseScratchRegisterScope::CanAcquireVfp() const {
  VfpRegList* available = assembler_->GetScratchVfpRegisterList();
  DCHECK_NOT_NULL(available);
  for (int index = 0; index < T::kNumRegisters; index++) {
    T reg = T::from_code(index);
    uint64_t mask = reg.ToVfpRegList();
    if ((*available & mask) == mask) {
      return true;
    }
  }
  return false;
}

template <typename T>
T UseScratchRegisterScope::AcquireVfp() {
  VfpRegList* available = assembler_->GetScratchVfpRegisterList();
  DCHECK_NOT_NULL(available);
  for (int index = 0; index < T::kNumRegisters; index++) {
    T reg = T::from_code(index);
    uint64_t mask = reg.ToVfpRegList();
    if ((*available & mask) == mask) {
      *available &= ~mask;
      return reg;
    }
  }
  UNREACHABLE();
}

448 449
}  // namespace internal
}  // namespace v8
450

451
#endif  // V8_ARM_ASSEMBLER_ARM_INL_H_