generic_macros_msa.h 147 KB
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/*
 * Copyright (c) 2015 Manojkumar Bhosale (Manojkumar.Bhosale@imgtec.com)
 *
 * This file is part of FFmpeg.
 *
 * FFmpeg is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * FFmpeg is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with FFmpeg; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 */

#ifndef AVUTIL_MIPS_GENERIC_MACROS_MSA_H
#define AVUTIL_MIPS_GENERIC_MACROS_MSA_H

#include <stdint.h>
#include <msa.h>

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#define ALIGNMENT           16
#define ALLOC_ALIGNED(align) __attribute__ ((aligned((align) << 1)))

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#define LD_V(RTYPE, psrc) *((RTYPE *)(psrc))
#define LD_UB(...) LD_V(v16u8, __VA_ARGS__)
#define LD_SB(...) LD_V(v16i8, __VA_ARGS__)
#define LD_UH(...) LD_V(v8u16, __VA_ARGS__)
#define LD_SH(...) LD_V(v8i16, __VA_ARGS__)
#define LD_UW(...) LD_V(v4u32, __VA_ARGS__)
#define LD_SW(...) LD_V(v4i32, __VA_ARGS__)

#define ST_V(RTYPE, in, pdst) *((RTYPE *)(pdst)) = (in)
#define ST_UB(...) ST_V(v16u8, __VA_ARGS__)
#define ST_SB(...) ST_V(v16i8, __VA_ARGS__)
#define ST_UH(...) ST_V(v8u16, __VA_ARGS__)
#define ST_SH(...) ST_V(v8i16, __VA_ARGS__)
#define ST_UW(...) ST_V(v4u32, __VA_ARGS__)
#define ST_SW(...) ST_V(v4i32, __VA_ARGS__)
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#if (__mips_isa_rev >= 6)
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    #define LH(psrc)                              \
    ( {                                           \
        uint16_t val_lh_m = *(uint16_t *)(psrc);  \
        val_lh_m;                                 \
    } )

    #define LW(psrc)                              \
    ( {                                           \
        uint32_t val_lw_m = *(uint32_t *)(psrc);  \
        val_lw_m;                                 \
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    } )

    #if (__mips == 64)
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        #define LD(psrc)                               \
        ( {                                            \
            uint64_t val_ld_m =  *(uint64_t *)(psrc);  \
            val_ld_m;                                  \
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        } )
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    #else  // !(__mips == 64)
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        #define LD(psrc)                                                    \
        ( {                                                                 \
            uint8_t *psrc_ld_m = (uint8_t *) (psrc);                        \
            uint32_t val0_ld_m, val1_ld_m;                                  \
            uint64_t val_ld_m = 0;                                          \
                                                                            \
            val0_ld_m = LW(psrc_ld_m);                                      \
            val1_ld_m = LW(psrc_ld_m + 4);                                  \
                                                                            \
            val_ld_m = (uint64_t) (val1_ld_m);                              \
            val_ld_m = (uint64_t) ((val_ld_m << 32) & 0xFFFFFFFF00000000);  \
            val_ld_m = (uint64_t) (val_ld_m | (uint64_t) val0_ld_m);        \
                                                                            \
            val_ld_m;                                                       \
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        } )
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    #endif  // (__mips == 64)

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    #define SH(val, pdst)  *(uint16_t *)(pdst) = (val);
    #define SW(val, pdst)  *(uint32_t *)(pdst) = (val);
    #define SD(val, pdst)  *(uint64_t *)(pdst) = (val);
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#else  // !(__mips_isa_rev >= 6)
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    #define LH(psrc)                                 \
    ( {                                              \
        uint8_t *psrc_lh_m = (uint8_t *) (psrc);     \
        uint16_t val_lh_m;                           \
                                                     \
        __asm__ volatile (                           \
            "ulh  %[val_lh_m],  %[psrc_lh_m]  \n\t"  \
                                                     \
            : [val_lh_m] "=r" (val_lh_m)             \
            : [psrc_lh_m] "m" (*psrc_lh_m)           \
        );                                           \
                                                     \
        val_lh_m;                                    \
    } )

    #define LW(psrc)                                 \
    ( {                                              \
        uint8_t *psrc_lw_m = (uint8_t *) (psrc);     \
        uint32_t val_lw_m;                           \
                                                     \
        __asm__ volatile (                           \
            "ulw  %[val_lw_m],  %[psrc_lw_m]  \n\t"  \
                                                     \
            : [val_lw_m] "=r" (val_lw_m)             \
            : [psrc_lw_m] "m" (*psrc_lw_m)           \
        );                                           \
                                                     \
        val_lw_m;                                    \
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    } )

    #if (__mips == 64)
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        #define LD(psrc)                                 \
        ( {                                              \
            uint8_t *psrc_ld_m = (uint8_t *) (psrc);     \
            uint64_t val_ld_m = 0;                       \
                                                         \
            __asm__ volatile (                           \
                "uld  %[val_ld_m],  %[psrc_ld_m]  \n\t"  \
                                                         \
                : [val_ld_m] "=r" (val_ld_m)             \
                : [psrc_ld_m] "m" (*psrc_ld_m)           \
            );                                           \
                                                         \
            val_ld_m;                                    \
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        } )
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    #else  // !(__mips == 64)
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        #define LD(psrc)                                                    \
        ( {                                                                 \
            uint8_t *psrc_ld_m = (uint8_t *) (psrc);                        \
            uint32_t val0_ld_m, val1_ld_m;                                  \
            uint64_t val_ld_m = 0;                                          \
                                                                            \
            val0_ld_m = LW(psrc_ld_m);                                      \
            val1_ld_m = LW(psrc_ld_m + 4);                                  \
                                                                            \
            val_ld_m = (uint64_t) (val1_ld_m);                              \
            val_ld_m = (uint64_t) ((val_ld_m << 32) & 0xFFFFFFFF00000000);  \
            val_ld_m = (uint64_t) (val_ld_m | (uint64_t) val0_ld_m);        \
                                                                            \
            val_ld_m;                                                       \
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        } )
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    #endif  // (__mips == 64)

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    #define SH(val, pdst)                            \
    {                                                \
        uint8_t *pdst_sh_m = (uint8_t *) (pdst);     \
        uint16_t val_sh_m = (val);                   \
                                                     \
        __asm__ volatile (                           \
            "ush  %[val_sh_m],  %[pdst_sh_m]  \n\t"  \
                                                     \
            : [pdst_sh_m] "=m" (*pdst_sh_m)          \
            : [val_sh_m] "r" (val_sh_m)              \
        );                                           \
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    }

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    #define SW(val, pdst)                            \
    {                                                \
        uint8_t *pdst_sw_m = (uint8_t *) (pdst);     \
        uint32_t val_sw_m = (val);                   \
                                                     \
        __asm__ volatile (                           \
            "usw  %[val_sw_m],  %[pdst_sw_m]  \n\t"  \
                                                     \
            : [pdst_sw_m] "=m" (*pdst_sw_m)          \
            : [val_sw_m] "r" (val_sw_m)              \
        );                                           \
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    }

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    #define SD(val, pdst)                                             \
    {                                                                 \
        uint8_t *pdst_sd_m = (uint8_t *) (pdst);                      \
        uint32_t val0_sd_m, val1_sd_m;                                \
                                                                      \
        val0_sd_m = (uint32_t) ((val) & 0x00000000FFFFFFFF);          \
        val1_sd_m = (uint32_t) (((val) >> 32) & 0x00000000FFFFFFFF);  \
                                                                      \
        SW(val0_sd_m, pdst_sd_m);                                     \
        SW(val1_sd_m, pdst_sd_m + 4);                                 \
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    }
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#endif // (__mips_isa_rev >= 6)

/* Description : Load 4 words with stride
   Arguments   : Inputs  - psrc    (source pointer to load from)
                         - stride
                 Outputs - out0, out1, out2, out3
   Details     : Loads word in 'out0' from (psrc)
                 Loads word in 'out1' from (psrc + stride)
                 Loads word in 'out2' from (psrc + 2 * stride)
                 Loads word in 'out3' from (psrc + 3 * stride)
*/
#define LW4(psrc, stride, out0, out1, out2, out3)  \
{                                                  \
    out0 = LW((psrc));                             \
    out1 = LW((psrc) + stride);                    \
    out2 = LW((psrc) + 2 * stride);                \
    out3 = LW((psrc) + 3 * stride);                \
}

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#define LW2(psrc, stride, out0, out1)  \
{                                      \
    out0 = LW((psrc));                 \
    out1 = LW((psrc) + stride);        \
}

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/* Description : Load double words with stride
   Arguments   : Inputs  - psrc    (source pointer to load from)
                         - stride
                 Outputs - out0, out1
   Details     : Loads double word in 'out0' from (psrc)
                 Loads double word in 'out1' from (psrc + stride)
*/
#define LD2(psrc, stride, out0, out1)  \
{                                      \
    out0 = LD((psrc));                 \
    out1 = LD((psrc) + stride);        \
}
#define LD4(psrc, stride, out0, out1, out2, out3)  \
{                                                  \
    LD2((psrc), stride, out0, out1);               \
    LD2((psrc) + 2 * stride, stride, out2, out3);  \
}

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/* Description : Store 4 words with stride
   Arguments   : Inputs  - in0, in1, in2, in3, pdst, stride
   Details     : Stores word from 'in0' to (pdst)
                 Stores word from 'in1' to (pdst + stride)
                 Stores word from 'in2' to (pdst + 2 * stride)
                 Stores word from 'in3' to (pdst + 3 * stride)
*/
#define SW4(in0, in1, in2, in3, pdst, stride)  \
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{                                              \
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    SW(in0, (pdst))                            \
    SW(in1, (pdst) + stride);                  \
    SW(in2, (pdst) + 2 * stride);              \
    SW(in3, (pdst) + 3 * stride);              \
}

/* Description : Store 4 double words with stride
   Arguments   : Inputs  - in0, in1, in2, in3, pdst, stride
   Details     : Stores double word from 'in0' to (pdst)
                 Stores double word from 'in1' to (pdst + stride)
                 Stores double word from 'in2' to (pdst + 2 * stride)
                 Stores double word from 'in3' to (pdst + 3 * stride)
*/
#define SD4(in0, in1, in2, in3, pdst, stride)  \
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{                                              \
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    SD(in0, (pdst))                            \
    SD(in1, (pdst) + stride);                  \
    SD(in2, (pdst) + 2 * stride);              \
    SD(in3, (pdst) + 3 * stride);              \
}

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/* Description : Load vector elements with stride
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   Arguments   : Inputs  - psrc    (source pointer to load from)
                         - stride
                 Outputs - out0, out1
                 Return Type - as per RTYPE
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   Details     : Loads elements in 'out0' from (psrc)
                 Loads elements in 'out1' from (psrc + stride)
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*/
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#define LD_V2(RTYPE, psrc, stride, out0, out1)  \
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{                                               \
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    out0 = LD_V(RTYPE, (psrc));                 \
    out1 = LD_V(RTYPE, (psrc) + stride);        \
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}
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#define LD_UB2(...) LD_V2(v16u8, __VA_ARGS__)
#define LD_SB2(...) LD_V2(v16i8, __VA_ARGS__)
#define LD_UH2(...) LD_V2(v8u16, __VA_ARGS__)
#define LD_SH2(...) LD_V2(v8i16, __VA_ARGS__)
#define LD_SW2(...) LD_V2(v4i32, __VA_ARGS__)
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#define LD_V3(RTYPE, psrc, stride, out0, out1, out2)  \
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{                                                     \
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    LD_V2(RTYPE, (psrc), stride, out0, out1);         \
    out2 = LD_V(RTYPE, (psrc) + 2 * stride);          \
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}
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#define LD_UB3(...) LD_V3(v16u8, __VA_ARGS__)
#define LD_SB3(...) LD_V3(v16i8, __VA_ARGS__)
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#define LD_V4(RTYPE, psrc, stride, out0, out1, out2, out3)   \
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{                                                            \
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    LD_V2(RTYPE, (psrc), stride, out0, out1);                \
    LD_V2(RTYPE, (psrc) + 2 * stride , stride, out2, out3);  \
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}
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#define LD_UB4(...) LD_V4(v16u8, __VA_ARGS__)
#define LD_SB4(...) LD_V4(v16i8, __VA_ARGS__)
#define LD_UH4(...) LD_V4(v8u16, __VA_ARGS__)
#define LD_SH4(...) LD_V4(v8i16, __VA_ARGS__)
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#define LD_V5(RTYPE, psrc, stride, out0, out1, out2, out3, out4)  \
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{                                                                 \
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    LD_V4(RTYPE, (psrc), stride, out0, out1, out2, out3);         \
    out4 = LD_V(RTYPE, (psrc) + 4 * stride);                      \
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}
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#define LD_UB5(...) LD_V5(v16u8, __VA_ARGS__)
#define LD_SB5(...) LD_V5(v16i8, __VA_ARGS__)
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#define LD_V6(RTYPE, psrc, stride, out0, out1, out2, out3, out4, out5)  \
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{                                                                       \
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    LD_V4(RTYPE, (psrc), stride, out0, out1, out2, out3);               \
    LD_V2(RTYPE, (psrc) + 4 * stride, stride, out4, out5);              \
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}
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#define LD_UB6(...) LD_V6(v16u8, __VA_ARGS__)
#define LD_SB6(...) LD_V6(v16i8, __VA_ARGS__)
#define LD_UH6(...) LD_V6(v8u16, __VA_ARGS__)
#define LD_SH6(...) LD_V6(v8i16, __VA_ARGS__)
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#define LD_V7(RTYPE, psrc, stride,                               \
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              out0, out1, out2, out3, out4, out5, out6)          \
{                                                                \
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    LD_V5(RTYPE, (psrc), stride, out0, out1, out2, out3, out4);  \
    LD_V2(RTYPE, (psrc) + 5 * stride, stride, out5, out6);       \
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}
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#define LD_UB7(...) LD_V7(v16u8, __VA_ARGS__)
#define LD_SB7(...) LD_V7(v16i8, __VA_ARGS__)
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#define LD_V8(RTYPE, psrc, stride,                                      \
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              out0, out1, out2, out3, out4, out5, out6, out7)           \
{                                                                       \
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    LD_V4(RTYPE, (psrc), stride, out0, out1, out2, out3);               \
    LD_V4(RTYPE, (psrc) + 4 * stride, stride, out4, out5, out6, out7);  \
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}
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#define LD_UB8(...) LD_V8(v16u8, __VA_ARGS__)
#define LD_SB8(...) LD_V8(v16i8, __VA_ARGS__)
#define LD_UH8(...) LD_V8(v8u16, __VA_ARGS__)
#define LD_SH8(...) LD_V8(v8i16, __VA_ARGS__)
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#define LD_V16(RTYPE, psrc, stride,                                   \
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               out0, out1, out2, out3, out4, out5, out6, out7,        \
               out8, out9, out10, out11, out12, out13, out14, out15)  \
{                                                                     \
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    LD_V8(RTYPE, (psrc), stride,                                      \
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          out0, out1, out2, out3, out4, out5, out6, out7);            \
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    LD_V8(RTYPE, (psrc) + 8 * stride, stride,                         \
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          out8, out9, out10, out11, out12, out13, out14, out15);      \
}
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#define LD_SH16(...) LD_V16(v8i16, __VA_ARGS__)
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/* Description : Load as 4x4 block of signed halfword elements from 1D source
                 data into 4 vectors (Each vector with 4 signed halfwords)
   Arguments   : Inputs  - psrc
                 Outputs - out0, out1, out2, out3
*/
#define LD4x4_SH(psrc, out0, out1, out2, out3)                \
{                                                             \
    out0 = LD_SH(psrc);                                       \
    out2 = LD_SH(psrc + 8);                                   \
    out1 = (v8i16) __msa_ilvl_d((v2i64) out0, (v2i64) out0);  \
    out3 = (v8i16) __msa_ilvl_d((v2i64) out2, (v2i64) out2);  \
}

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/* Description : Store vectors with stride
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   Arguments   : Inputs  - in0, in1, stride
                 Outputs - pdst    (destination pointer to store to)
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   Details     : Stores elements from 'in0' to (pdst)
                 Stores elements from 'in1' to (pdst + stride)
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*/
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#define ST_V2(RTYPE, in0, in1, pdst, stride)  \
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{                                             \
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    ST_V(RTYPE, in0, (pdst));                 \
    ST_V(RTYPE, in1, (pdst) + stride);        \
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}
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#define ST_UB2(...) ST_V2(v16u8, __VA_ARGS__)
#define ST_SB2(...) ST_V2(v16i8, __VA_ARGS__)
#define ST_UH2(...) ST_V2(v8u16, __VA_ARGS__)
#define ST_SH2(...) ST_V2(v8i16, __VA_ARGS__)
#define ST_SW2(...) ST_V2(v4i32, __VA_ARGS__)
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#define ST_V4(RTYPE, in0, in1, in2, in3, pdst, stride)    \
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{                                                         \
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    ST_V2(RTYPE, in0, in1, (pdst), stride);               \
    ST_V2(RTYPE, in2, in3, (pdst) + 2 * stride, stride);  \
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}
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#define ST_UB4(...) ST_V4(v16u8, __VA_ARGS__)
#define ST_SB4(...) ST_V4(v16i8, __VA_ARGS__)
#define ST_SH4(...) ST_V4(v8i16, __VA_ARGS__)
#define ST_SW4(...) ST_V4(v4i32, __VA_ARGS__)
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#define ST_V6(RTYPE, in0, in1, in2, in3, in4, in5, pdst, stride)  \
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{                                                                 \
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    ST_V4(RTYPE, in0, in1, in2, in3, (pdst), stride);             \
    ST_V2(RTYPE, in4, in5, (pdst) + 4 * stride, stride);          \
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}
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#define ST_SH6(...) ST_V6(v8i16, __VA_ARGS__)
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#define ST_V8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride)  \
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{                                                                           \
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    ST_V4(RTYPE, in0, in1, in2, in3, (pdst), stride);                       \
    ST_V4(RTYPE, in4, in5, in6, in7, (pdst) + 4 * stride, stride);          \
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}
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#define ST_UB8(...) ST_V8(v16u8, __VA_ARGS__)
#define ST_SH8(...) ST_V8(v8i16, __VA_ARGS__)
#define ST_SW8(...) ST_V8(v4i32, __VA_ARGS__)
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/* Description : Store as 2x4 byte block to destination memory from input vector
   Arguments   : Inputs  - in, stidx, pdst, stride
                 Return Type - unsigned byte
   Details     : Index stidx halfword element from 'in' vector is copied and
                 stored on first line
                 Index stidx+1 halfword element from 'in' vector is copied and
                 stored on second line
                 Index stidx+2 halfword element from 'in' vector is copied and
                 stored on third line
                 Index stidx+3 halfword element from 'in' vector is copied and
                 stored on fourth line
*/
#define ST2x4_UB(in, stidx, pdst, stride)              \
{                                                      \
    uint16_t out0_m, out1_m, out2_m, out3_m;           \
    uint8_t *pblk_2x4_m = (uint8_t *) (pdst);          \
                                                       \
    out0_m = __msa_copy_u_h((v8i16) in, (stidx));      \
    out1_m = __msa_copy_u_h((v8i16) in, (stidx + 1));  \
    out2_m = __msa_copy_u_h((v8i16) in, (stidx + 2));  \
    out3_m = __msa_copy_u_h((v8i16) in, (stidx + 3));  \
                                                       \
    SH(out0_m, pblk_2x4_m);                            \
    SH(out1_m, pblk_2x4_m + stride);                   \
    SH(out2_m, pblk_2x4_m + 2 * stride);               \
    SH(out3_m, pblk_2x4_m + 3 * stride);               \
}

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/* Description : Store as 4x2 byte block to destination memory from input vector
   Arguments   : Inputs  - in, pdst, stride
                 Return Type - unsigned byte
   Details     : Index 0 word element from input vector is copied and stored
                 on first line
                 Index 1 word element from input vector is copied and stored
                 on second line
*/
#define ST4x2_UB(in, pdst, stride)             \
{                                              \
    uint32_t out0_m, out1_m;                   \
    uint8_t *pblk_4x2_m = (uint8_t *) (pdst);  \
                                               \
    out0_m = __msa_copy_u_w((v4i32) in, 0);    \
    out1_m = __msa_copy_u_w((v4i32) in, 1);    \
                                               \
    SW(out0_m, pblk_4x2_m);                    \
    SW(out1_m, pblk_4x2_m + stride);           \
}

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/* Description : Store as 4x4 byte block to destination memory from input vector
   Arguments   : Inputs  - in0, in1, pdst, stride
                 Return Type - unsigned byte
   Details     : Idx0 word element from input vector 'in0' is copied and stored
                 on first line
                 Idx1 word element from input vector 'in0' is copied and stored
                 on second line
                 Idx2 word element from input vector 'in1' is copied and stored
                 on third line
                 Idx3 word element from input vector 'in1' is copied and stored
                 on fourth line
*/
#define ST4x4_UB(in0, in1, idx0, idx1, idx2, idx3, pdst, stride)  \
{                                                                 \
    uint32_t out0_m, out1_m, out2_m, out3_m;                      \
    uint8_t *pblk_4x4_m = (uint8_t *) (pdst);                     \
                                                                  \
    out0_m = __msa_copy_u_w((v4i32) in0, idx0);                   \
    out1_m = __msa_copy_u_w((v4i32) in0, idx1);                   \
    out2_m = __msa_copy_u_w((v4i32) in1, idx2);                   \
    out3_m = __msa_copy_u_w((v4i32) in1, idx3);                   \
                                                                  \
    SW4(out0_m, out1_m, out2_m, out3_m, pblk_4x4_m, stride);      \
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}
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#define ST4x8_UB(in0, in1, pdst, stride)                            \
{                                                                   \
    uint8_t *pblk_4x8 = (uint8_t *) (pdst);                         \
                                                                    \
    ST4x4_UB(in0, in0, 0, 1, 2, 3, pblk_4x8, stride);               \
    ST4x4_UB(in1, in1, 0, 1, 2, 3, pblk_4x8 + 4 * stride, stride);  \
}

/* Description : Store as 6x4 byte block to destination memory from input
                 vectors
   Arguments   : Inputs  - in0, in1, pdst, stride
                 Return Type - unsigned byte
   Details     : Index 0 word element from input vector 'in0' is copied and
                 stored on first line followed by index 2 halfword element
                 Index 2 word element from input vector 'in0' is copied and
                 stored on second line followed by index 2 halfword element
                 Index 0 word element from input vector 'in1' is copied and
                 stored on third line followed by index 2 halfword element
                 Index 2 word element from input vector 'in1' is copied and
                 stored on fourth line followed by index 2 halfword element
*/
#define ST6x4_UB(in0, in1, pdst, stride)       \
{                                              \
    uint32_t out0_m, out1_m, out2_m, out3_m;   \
    uint16_t out4_m, out5_m, out6_m, out7_m;   \
    uint8_t *pblk_6x4_m = (uint8_t *) (pdst);  \
                                               \
    out0_m = __msa_copy_u_w((v4i32) in0, 0);   \
    out1_m = __msa_copy_u_w((v4i32) in0, 2);   \
    out2_m = __msa_copy_u_w((v4i32) in1, 0);   \
    out3_m = __msa_copy_u_w((v4i32) in1, 2);   \
                                               \
    out4_m = __msa_copy_u_h((v8i16) in0, 2);   \
    out5_m = __msa_copy_u_h((v8i16) in0, 6);   \
    out6_m = __msa_copy_u_h((v8i16) in1, 2);   \
    out7_m = __msa_copy_u_h((v8i16) in1, 6);   \
                                               \
    SW(out0_m, pblk_6x4_m);                    \
    SH(out4_m, (pblk_6x4_m + 4));              \
    pblk_6x4_m += stride;                      \
    SW(out1_m, pblk_6x4_m);                    \
    SH(out5_m, (pblk_6x4_m + 4));              \
    pblk_6x4_m += stride;                      \
    SW(out2_m, pblk_6x4_m);                    \
    SH(out6_m, (pblk_6x4_m + 4));              \
    pblk_6x4_m += stride;                      \
    SW(out3_m, pblk_6x4_m);                    \
    SH(out7_m, (pblk_6x4_m + 4));              \
}
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/* Description : Store as 8x1 byte block to destination memory from input vector
   Arguments   : Inputs  - in, pdst
   Details     : Index 0 double word element from input vector 'in' is copied
                 and stored to destination memory at (pdst)
*/
#define ST8x1_UB(in, pdst)                   \
{                                            \
    uint64_t out0_m;                         \
    out0_m = __msa_copy_u_d((v2i64) in, 0);  \
    SD(out0_m, pdst);                        \
}

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/* Description : Store as 8x2 byte block to destination memory from input vector
   Arguments   : Inputs  - in, pdst, stride
   Details     : Index 0 double word element from input vector 'in' is copied
                 and stored to destination memory at (pdst)
                 Index 1 double word element from input vector 'in' is copied
                 and stored to destination memory at (pdst + stride)
*/
#define ST8x2_UB(in, pdst, stride)             \
{                                              \
    uint64_t out0_m, out1_m;                   \
    uint8_t *pblk_8x2_m = (uint8_t *) (pdst);  \
                                               \
    out0_m = __msa_copy_u_d((v2i64) in, 0);    \
    out1_m = __msa_copy_u_d((v2i64) in, 1);    \
                                               \
    SD(out0_m, pblk_8x2_m);                    \
    SD(out1_m, pblk_8x2_m + stride);           \
}

/* Description : Store as 8x4 byte block to destination memory from input
                 vectors
   Arguments   : Inputs  - in0, in1, pdst, stride
   Details     : Index 0 double word element from input vector 'in0' is copied
                 and stored to destination memory at (pblk_8x4_m)
                 Index 1 double word element from input vector 'in0' is copied
                 and stored to destination memory at (pblk_8x4_m + stride)
                 Index 0 double word element from input vector 'in1' is copied
                 and stored to destination memory at (pblk_8x4_m + 2 * stride)
                 Index 1 double word element from input vector 'in1' is copied
                 and stored to destination memory at (pblk_8x4_m + 3 * stride)
*/
#define ST8x4_UB(in0, in1, pdst, stride)                      \
{                                                             \
    uint64_t out0_m, out1_m, out2_m, out3_m;                  \
    uint8_t *pblk_8x4_m = (uint8_t *) (pdst);                 \
                                                              \
    out0_m = __msa_copy_u_d((v2i64) in0, 0);                  \
    out1_m = __msa_copy_u_d((v2i64) in0, 1);                  \
    out2_m = __msa_copy_u_d((v2i64) in1, 0);                  \
    out3_m = __msa_copy_u_d((v2i64) in1, 1);                  \
                                                              \
    SD4(out0_m, out1_m, out2_m, out3_m, pblk_8x4_m, stride);  \
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}
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#define ST8x8_UB(in0, in1, in2, in3, pdst, stride)        \
{                                                         \
    uint8_t *pblk_8x8_m = (uint8_t *) (pdst);             \
                                                          \
    ST8x4_UB(in0, in1, pblk_8x8_m, stride);               \
    ST8x4_UB(in2, in3, pblk_8x8_m + 4 * stride, stride);  \
}
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#define ST12x4_UB(in0, in1, in2, pdst, stride)                \
{                                                             \
    uint8_t *pblk_12x4_m = (uint8_t *) (pdst);                \
                                                              \
    /* left 8x4 */                                            \
    ST8x4_UB(in0, in1, pblk_12x4_m, stride);                  \
    /* right 4x4 */                                           \
    ST4x4_UB(in2, in2, 0, 1, 2, 3, pblk_12x4_m + 8, stride);  \
}
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/* Description : Store as 12x8 byte block to destination memory from
                 input vectors
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride
   Details     : Index 0 double word element from input vector 'in0' is copied
                 and stored to destination memory at (pblk_12x8_m) followed by
                 index 2 word element from same input vector 'in0' at
                 (pblk_12x8_m + 8)
                 Similar to remaining lines
*/
#define ST12x8_UB(in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride)  \
{                                                                        \
    uint64_t out0_m, out1_m, out2_m, out3_m;                             \
    uint64_t out4_m, out5_m, out6_m, out7_m;                             \
    uint32_t out8_m, out9_m, out10_m, out11_m;                           \
    uint32_t out12_m, out13_m, out14_m, out15_m;                         \
    uint8_t *pblk_12x8_m = (uint8_t *) (pdst);                           \
                                                                         \
    out0_m = __msa_copy_u_d((v2i64) in0, 0);                             \
    out1_m = __msa_copy_u_d((v2i64) in1, 0);                             \
    out2_m = __msa_copy_u_d((v2i64) in2, 0);                             \
    out3_m = __msa_copy_u_d((v2i64) in3, 0);                             \
    out4_m = __msa_copy_u_d((v2i64) in4, 0);                             \
    out5_m = __msa_copy_u_d((v2i64) in5, 0);                             \
    out6_m = __msa_copy_u_d((v2i64) in6, 0);                             \
    out7_m = __msa_copy_u_d((v2i64) in7, 0);                             \
                                                                         \
    out8_m =  __msa_copy_u_w((v4i32) in0, 2);                            \
    out9_m =  __msa_copy_u_w((v4i32) in1, 2);                            \
    out10_m = __msa_copy_u_w((v4i32) in2, 2);                            \
    out11_m = __msa_copy_u_w((v4i32) in3, 2);                            \
    out12_m = __msa_copy_u_w((v4i32) in4, 2);                            \
    out13_m = __msa_copy_u_w((v4i32) in5, 2);                            \
    out14_m = __msa_copy_u_w((v4i32) in6, 2);                            \
    out15_m = __msa_copy_u_w((v4i32) in7, 2);                            \
                                                                         \
    SD(out0_m, pblk_12x8_m);                                             \
    SW(out8_m, pblk_12x8_m + 8);                                         \
    pblk_12x8_m += stride;                                               \
    SD(out1_m, pblk_12x8_m);                                             \
    SW(out9_m, pblk_12x8_m + 8);                                         \
    pblk_12x8_m += stride;                                               \
    SD(out2_m, pblk_12x8_m);                                             \
    SW(out10_m, pblk_12x8_m + 8);                                        \
    pblk_12x8_m += stride;                                               \
    SD(out3_m, pblk_12x8_m);                                             \
    SW(out11_m, pblk_12x8_m + 8);                                        \
    pblk_12x8_m += stride;                                               \
    SD(out4_m, pblk_12x8_m);                                             \
    SW(out12_m, pblk_12x8_m + 8);                                        \
    pblk_12x8_m += stride;                                               \
    SD(out5_m, pblk_12x8_m);                                             \
    SW(out13_m, pblk_12x8_m + 8);                                        \
    pblk_12x8_m += stride;                                               \
    SD(out6_m, pblk_12x8_m);                                             \
    SW(out14_m, pblk_12x8_m + 8);                                        \
    pblk_12x8_m += stride;                                               \
    SD(out7_m, pblk_12x8_m);                                             \
    SW(out15_m, pblk_12x8_m + 8);                                        \
}

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/* Description : average with rounding (in0 + in1 + 1) / 2.
   Arguments   : Inputs  - in0, in1, in2, in3,
                 Outputs - out0, out1
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                 Return Type - as per RTYPE
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   Details     : Each byte element from 'in0' vector is added with each byte
                 element from 'in1' vector. The addition of the elements plus 1
                (for rounding) is done unsigned with full precision,
                i.e. the result has one extra bit. Unsigned division by 2
                (or logical shift right by one bit) is performed before writing
                the result to vector 'out0'
                Similar for the pair of 'in2' and 'in3'
*/
#define AVER_UB2(RTYPE, in0, in1, in2, in3, out0, out1)       \
{                                                             \
    out0 = (RTYPE) __msa_aver_u_b((v16u8) in0, (v16u8) in1);  \
    out1 = (RTYPE) __msa_aver_u_b((v16u8) in2, (v16u8) in3);  \
}
#define AVER_UB2_UB(...) AVER_UB2(v16u8, __VA_ARGS__)

#define AVER_UB4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
                 out0, out1, out2, out3)                        \
{                                                               \
    AVER_UB2(RTYPE, in0, in1, in2, in3, out0, out1)             \
    AVER_UB2(RTYPE, in4, in5, in6, in7, out2, out3)             \
}
#define AVER_UB4_UB(...) AVER_UB4(v16u8, __VA_ARGS__)

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/* Description : Immediate number of columns to slide with zero
   Arguments   : Inputs  - in0, in1, slide_val
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Byte elements from 'zero_m' vector are slide into 'in0' by
                 number of elements specified by 'slide_val'
*/
#define SLDI_B2_0(RTYPE, in0, in1, out0, out1, slide_val)                 \
{                                                                         \
    v16i8 zero_m = { 0 };                                                 \
    out0 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in0, slide_val);  \
    out1 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in1, slide_val);  \
}
#define SLDI_B2_0_UB(...) SLDI_B2_0(v16u8, __VA_ARGS__)
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#define SLDI_B2_0_SB(...) SLDI_B2_0(v16i8, __VA_ARGS__)
#define SLDI_B2_0_SW(...) SLDI_B2_0(v4i32, __VA_ARGS__)
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#define SLDI_B3_0(RTYPE, in0, in1, in2, out0, out1, out2,  slide_val)     \
{                                                                         \
    v16i8 zero_m = { 0 };                                                 \
    SLDI_B2_0(RTYPE, in0, in1, out0, out1, slide_val);                    \
    out2 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in2, slide_val);  \
}
#define SLDI_B3_0_UB(...) SLDI_B3_0(v16u8, __VA_ARGS__)
#define SLDI_B3_0_SB(...) SLDI_B3_0(v16i8, __VA_ARGS__)

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#define SLDI_B4_0(RTYPE, in0, in1, in2, in3,            \
                  out0, out1, out2, out3, slide_val)    \
{                                                       \
    SLDI_B2_0(RTYPE, in0, in1, out0, out1, slide_val);  \
    SLDI_B2_0(RTYPE, in2, in3, out2, out3, slide_val);  \
}
716
#define SLDI_B4_0_UB(...) SLDI_B4_0(v16u8, __VA_ARGS__)
717
#define SLDI_B4_0_SB(...) SLDI_B4_0(v16i8, __VA_ARGS__)
718
#define SLDI_B4_0_SH(...) SLDI_B4_0(v8i16, __VA_ARGS__)
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/* Description : Immediate number of columns to slide
   Arguments   : Inputs  - in0_0, in0_1, in1_0, in1_1, slide_val
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Byte elements from 'in0_0' vector are slide into 'in1_0' by
                 number of elements specified by 'slide_val'
*/
#define SLDI_B2(RTYPE, in0_0, in0_1, in1_0, in1_1, out0, out1, slide_val)  \
{                                                                          \
    out0 = (RTYPE) __msa_sldi_b((v16i8) in0_0, (v16i8) in1_0, slide_val);  \
    out1 = (RTYPE) __msa_sldi_b((v16i8) in0_1, (v16i8) in1_1, slide_val);  \
}
#define SLDI_B2_UB(...) SLDI_B2(v16u8, __VA_ARGS__)
#define SLDI_B2_SB(...) SLDI_B2(v16i8, __VA_ARGS__)
#define SLDI_B2_SH(...) SLDI_B2(v8i16, __VA_ARGS__)

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#define SLDI_B3(RTYPE, in0_0, in0_1, in0_2, in1_0, in1_1, in1_2,           \
                out0, out1, out2, slide_val)                               \
{                                                                          \
    SLDI_B2(RTYPE, in0_0, in0_1, in1_0, in1_1, out0, out1, slide_val)      \
    out2 = (RTYPE) __msa_sldi_b((v16i8) in0_2, (v16i8) in1_2, slide_val);  \
}
#define SLDI_B3_SB(...) SLDI_B3(v16i8, __VA_ARGS__)
#define SLDI_B3_UH(...) SLDI_B3(v8u16, __VA_ARGS__)
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/* Description : Shuffle byte vector elements as per mask vector
   Arguments   : Inputs  - in0, in1, in2, in3, mask0, mask1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Selective byte elements from in0 & in1 are copied to out0 as
                 per control vector mask0
                 Selective byte elements from in2 & in3 are copied to out1 as
                 per control vector mask1
*/
#define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1)       \
{                                                                          \
    out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0);  \
    out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2);  \
758
}
759
#define VSHF_B2_UB(...) VSHF_B2(v16u8, __VA_ARGS__)
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#define VSHF_B2_SB(...) VSHF_B2(v16i8, __VA_ARGS__)
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#define VSHF_B2_UH(...) VSHF_B2(v8u16, __VA_ARGS__)
#define VSHF_B2_SH(...) VSHF_B2(v8i16, __VA_ARGS__)

#define VSHF_B3(RTYPE, in0, in1, in2, in3, in4, in5, mask0, mask1, mask2,  \
                out0, out1, out2)                                          \
{                                                                          \
    VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1);          \
    out2 = (RTYPE) __msa_vshf_b((v16i8) mask2, (v16i8) in5, (v16i8) in4);  \
}
#define VSHF_B3_SB(...) VSHF_B3(v16i8, __VA_ARGS__)
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#define VSHF_B4(RTYPE, in0, in1, mask0, mask1, mask2, mask3,       \
                out0, out1, out2, out3)                            \
{                                                                  \
    VSHF_B2(RTYPE, in0, in1, in0, in1, mask0, mask1, out0, out1);  \
    VSHF_B2(RTYPE, in0, in1, in0, in1, mask2, mask3, out2, out3);  \
}
#define VSHF_B4_SB(...) VSHF_B4(v16i8, __VA_ARGS__)
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#define VSHF_B4_SH(...) VSHF_B4(v8i16, __VA_ARGS__)

/* Description : Shuffle halfword vector elements as per mask vector
   Arguments   : Inputs  - in0, in1, in2, in3, mask0, mask1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Selective halfword elements from in0 & in1 are copied to out0
                 as per control vector mask0
                 Selective halfword elements from in2 & in3 are copied to out1
                 as per control vector mask1
*/
#define VSHF_H2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1)       \
{                                                                          \
    out0 = (RTYPE) __msa_vshf_h((v8i16) mask0, (v8i16) in1, (v8i16) in0);  \
    out1 = (RTYPE) __msa_vshf_h((v8i16) mask1, (v8i16) in3, (v8i16) in2);  \
}
#define VSHF_H2_SH(...) VSHF_H2(v8i16, __VA_ARGS__)
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#define VSHF_H3(RTYPE, in0, in1, in2, in3, in4, in5, mask0, mask1, mask2,  \
                out0, out1, out2)                                          \
{                                                                          \
    VSHF_H2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1);          \
    out2 = (RTYPE) __msa_vshf_h((v8i16) mask2, (v8i16) in5, (v8i16) in4);  \
}
#define VSHF_H3_SH(...) VSHF_H3(v8i16, __VA_ARGS__)

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/* Description : Shuffle byte vector elements as per mask vector
   Arguments   : Inputs  - in0, in1, in2, in3, mask0, mask1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Selective byte elements from in0 & in1 are copied to out0 as
                 per control vector mask0
                 Selective byte elements from in2 & in3 are copied to out1 as
                 per control vector mask1
*/
#define VSHF_W2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1)      \
{                                                                         \
    out0 = (RTYPE) __msa_vshf_w((v4i32) mask0, (v4i32) in1, (v4i32) in0); \
    out1 = (RTYPE) __msa_vshf_w((v4i32) mask1, (v4i32) in3, (v4i32) in2); \
}
#define VSHF_W2_SB(...) VSHF_W2(v16i8, __VA_ARGS__)

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/* Description : Dot product of byte vector elements
   Arguments   : Inputs  - mult0, mult1
                           cnst0, cnst1
                 Outputs - out0, out1
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                 Return Type - as per RTYPE
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   Details     : Unsigned byte elements from mult0 are multiplied with
                 unsigned byte elements from cnst0 producing a result
                 twice the size of input i.e. unsigned halfword.
                 Then this multiplication results of adjacent odd-even elements
                 are added together and stored to the out vector
                 (2 unsigned halfword results)
*/
#define DOTP_UB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1)   \
{                                                                 \
    out0 = (RTYPE) __msa_dotp_u_h((v16u8) mult0, (v16u8) cnst0);  \
    out1 = (RTYPE) __msa_dotp_u_h((v16u8) mult1, (v16u8) cnst1);  \
}
#define DOTP_UB2_UH(...) DOTP_UB2(v8u16, __VA_ARGS__)

#define DOTP_UB4(RTYPE, mult0, mult1, mult2, mult3,           \
                 cnst0, cnst1, cnst2, cnst3,                  \
                 out0, out1, out2, out3)                      \
{                                                             \
    DOTP_UB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1);  \
    DOTP_UB2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3);  \
}
#define DOTP_UB4_UH(...) DOTP_UB4(v8u16, __VA_ARGS__)

849 850 851 852
/* Description : Dot product of byte vector elements
   Arguments   : Inputs  - mult0, mult1
                           cnst0, cnst1
                 Outputs - out0, out1
853
                 Return Type - as per RTYPE
854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883
   Details     : Signed byte elements from mult0 are multiplied with
                 signed byte elements from cnst0 producing a result
                 twice the size of input i.e. signed halfword.
                 Then this multiplication results of adjacent odd-even elements
                 are added together and stored to the out vector
                 (2 signed halfword results)
*/
#define DOTP_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1)   \
{                                                                 \
    out0 = (RTYPE) __msa_dotp_s_h((v16i8) mult0, (v16i8) cnst0);  \
    out1 = (RTYPE) __msa_dotp_s_h((v16i8) mult1, (v16i8) cnst1);  \
}
#define DOTP_SB2_SH(...) DOTP_SB2(v8i16, __VA_ARGS__)

#define DOTP_SB3(RTYPE, mult0, mult1, mult2, cnst0, cnst1, cnst2,  \
                 out0, out1, out2)                                 \
{                                                                  \
    DOTP_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1);       \
    out2 = (RTYPE) __msa_dotp_s_h((v16i8) mult2, (v16i8) cnst2);   \
}
#define DOTP_SB3_SH(...) DOTP_SB3(v8i16, __VA_ARGS__)

#define DOTP_SB4(RTYPE, mult0, mult1, mult2, mult3,                   \
                 cnst0, cnst1, cnst2, cnst3, out0, out1, out2, out3)  \
{                                                                     \
    DOTP_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1);          \
    DOTP_SB2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3);          \
}
#define DOTP_SB4_SH(...) DOTP_SB4(v8i16, __VA_ARGS__)

884 885 886 887
/* Description : Dot product of halfword vector elements
   Arguments   : Inputs  - mult0, mult1
                           cnst0, cnst1
                 Outputs - out0, out1
888
                 Return Type - as per RTYPE
889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911
   Details     : Signed halfword elements from mult0 are multiplied with
                 signed halfword elements from cnst0 producing a result
                 twice the size of input i.e. signed word.
                 Then this multiplication results of adjacent odd-even elements
                 are added together and stored to the out vector
                 (2 signed word results)
*/
#define DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1)   \
{                                                                 \
    out0 = (RTYPE) __msa_dotp_s_w((v8i16) mult0, (v8i16) cnst0);  \
    out1 = (RTYPE) __msa_dotp_s_w((v8i16) mult1, (v8i16) cnst1);  \
}
#define DOTP_SH2_SW(...) DOTP_SH2(v4i32, __VA_ARGS__)

#define DOTP_SH4(RTYPE, mult0, mult1, mult2, mult3,           \
                 cnst0, cnst1, cnst2, cnst3,                  \
                 out0, out1, out2, out3)                      \
{                                                             \
    DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1);  \
    DOTP_SH2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3);  \
}
#define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__)

912 913 914 915
/* Description : Dot product & addition of byte vector elements
   Arguments   : Inputs  - mult0, mult1
                           cnst0, cnst1
                 Outputs - out0, out1
916
                 Return Type - as per RTYPE
917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940
   Details     : Signed byte elements from mult0 are multiplied with
                 signed byte elements from cnst0 producing a result
                 twice the size of input i.e. signed halfword.
                 Then this multiplication results of adjacent odd-even elements
                 are added to the out vector
                 (2 signed halfword results)
*/
#define DPADD_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1)   \
{                                                                  \
    out0 = (RTYPE) __msa_dpadd_s_h((v8i16) out0,                   \
                                   (v16i8) mult0, (v16i8) cnst0);  \
    out1 = (RTYPE) __msa_dpadd_s_h((v8i16) out1,                   \
                                   (v16i8) mult1, (v16i8) cnst1);  \
}
#define DPADD_SB2_SH(...) DPADD_SB2(v8i16, __VA_ARGS__)

#define DPADD_SB4(RTYPE, mult0, mult1, mult2, mult3,                   \
                  cnst0, cnst1, cnst2, cnst3, out0, out1, out2, out3)  \
{                                                                      \
    DPADD_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1);          \
    DPADD_SB2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3);          \
}
#define DPADD_SB4_SH(...) DPADD_SB4(v8i16, __VA_ARGS__)

941 942 943 944
/* Description : Dot product & addition of byte vector elements
   Arguments   : Inputs  - mult0, mult1
                           cnst0, cnst1
                 Outputs - out0, out1
945
                 Return Type - as per RTYPE
946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961
   Details     : Unsigned byte elements from mult0 are multiplied with
                 unsigned byte elements from cnst0 producing a result
                 twice the size of input i.e. unsigned halfword.
                 Then this multiplication results of adjacent odd-even elements
                 are added to the out vector
                 (2 unsigned halfword results)
*/
#define DPADD_UB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1)   \
{                                                                  \
    out0 = (RTYPE) __msa_dpadd_u_h((v8u16) out0,                   \
                                   (v16u8) mult0, (v16u8) cnst0);  \
    out1 = (RTYPE) __msa_dpadd_u_h((v8u16) out1,                   \
                                   (v16u8) mult1, (v16u8) cnst1);  \
}
#define DPADD_UB2_UH(...) DPADD_UB2(v8u16, __VA_ARGS__)

962 963 964 965
/* Description : Dot product & addition of halfword vector elements
   Arguments   : Inputs  - mult0, mult1
                           cnst0, cnst1
                 Outputs - out0, out1
966
                 Return Type - as per RTYPE
967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982
   Details     : Signed halfword elements from mult0 are multiplied with
                 signed halfword elements from cnst0 producing a result
                 twice the size of input i.e. signed word.
                 Then this multiplication results of adjacent odd-even elements
                 are added to the out vector
                 (2 signed word results)
*/
#define DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1)   \
{                                                                  \
    out0 = (RTYPE) __msa_dpadd_s_w((v4i32) out0,                   \
                                   (v8i16) mult0, (v8i16) cnst0);  \
    out1 = (RTYPE) __msa_dpadd_s_w((v4i32) out1,                   \
                                   (v8i16) mult1, (v8i16) cnst1);  \
}
#define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__)

983 984 985 986 987 988 989 990
#define DPADD_SH4(RTYPE, mult0, mult1, mult2, mult3,                   \
                  cnst0, cnst1, cnst2, cnst3, out0, out1, out2, out3)  \
{                                                                      \
    DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1);          \
    DPADD_SH2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3);          \
}
#define DPADD_SH4_SW(...) DPADD_SH4(v4i32, __VA_ARGS__)

991 992 993 994
/* Description : Minimum values between unsigned elements of
                 either vector are copied to the output vector
   Arguments   : Inputs  - in0, in1, min_vec
                 Outputs - in0, in1, (in place)
995
                 Return Type - as per RTYPE
996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
   Details     : Minimum of unsigned halfword element values from 'in0' and
                 'min_value' are written to output vector 'in0'
*/
#define MIN_UH2(RTYPE, in0, in1, min_vec)               \
{                                                       \
    in0 = (RTYPE) __msa_min_u_h((v8u16) in0, min_vec);  \
    in1 = (RTYPE) __msa_min_u_h((v8u16) in1, min_vec);  \
}
#define MIN_UH2_UH(...) MIN_UH2(v8u16, __VA_ARGS__)

#define MIN_UH4(RTYPE, in0, in1, in2, in3, min_vec)  \
{                                                    \
    MIN_UH2(RTYPE, in0, in1, min_vec);               \
    MIN_UH2(RTYPE, in2, in3, min_vec);               \
}
#define MIN_UH4_UH(...) MIN_UH4(v8u16, __VA_ARGS__)

1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
/* Description : Clips all halfword elements of input vector between min & max
                 out = ((in) < (min)) ? (min) : (((in) > (max)) ? (max) : (in))
   Arguments   : Inputs  - in       (input vector)
                         - min      (min threshold)
                         - max      (max threshold)
                 Outputs - out_m    (output vector with clipped elements)
                 Return Type - signed halfword
*/
#define CLIP_SH(in, min, max)                           \
( {                                                     \
    v8i16 out_m;                                        \
                                                        \
    out_m = __msa_max_s_h((v8i16) min, (v8i16) in);     \
    out_m = __msa_min_s_h((v8i16) max, (v8i16) out_m);  \
    out_m;                                              \
1028 1029
} )

1030 1031 1032 1033 1034 1035 1036
/* Description : Clips all signed halfword elements of input vector
                 between 0 & 255
   Arguments   : Inputs  - in       (input vector)
                 Outputs - out_m    (output vector with clipped elements)
                 Return Type - signed halfword
*/
#define CLIP_SH_0_255(in)                                 \
1037 1038 1039 1040
( {                                                       \
    v8i16 max_m = __msa_ldi_h(255);                       \
    v8i16 out_m;                                          \
                                                          \
1041
    out_m = __msa_maxi_s_h((v8i16) in, 0);                \
1042 1043 1044
    out_m = __msa_min_s_h((v8i16) max_m, (v8i16) out_m);  \
    out_m;                                                \
} )
1045 1046 1047 1048
#define CLIP_SH2_0_255(in0, in1)  \
{                                 \
    in0 = CLIP_SH_0_255(in0);     \
    in1 = CLIP_SH_0_255(in1);     \
1049
}
1050 1051 1052 1053 1054 1055
#define CLIP_SH4_0_255(in0, in1, in2, in3)  \
{                                           \
    CLIP_SH2_0_255(in0, in1);               \
    CLIP_SH2_0_255(in2, in3);               \
}

1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074
#define CLIP_SH_0_255_MAX_SATU(in)                    \
( {                                                   \
    v8i16 out_m;                                      \
                                                      \
    out_m = __msa_maxi_s_h((v8i16) in, 0);            \
    out_m = (v8i16) __msa_sat_u_h((v8u16) out_m, 7);  \
    out_m;                                            \
} )
#define CLIP_SH2_0_255_MAX_SATU(in0, in1)  \
{                                          \
    in0 = CLIP_SH_0_255_MAX_SATU(in0);     \
    in1 = CLIP_SH_0_255_MAX_SATU(in1);     \
}
#define CLIP_SH4_0_255_MAX_SATU(in0, in1, in2, in3)  \
{                                                    \
    CLIP_SH2_0_255_MAX_SATU(in0, in1);               \
    CLIP_SH2_0_255_MAX_SATU(in2, in3);               \
}

1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
/* Description : Clips all signed word elements of input vector
                 between 0 & 255
   Arguments   : Inputs  - in       (input vector)
                 Outputs - out_m    (output vector with clipped elements)
                 Return Type - signed word
*/
#define CLIP_SW_0_255(in)                                 \
( {                                                       \
    v4i32 max_m = __msa_ldi_w(255);                       \
    v4i32 out_m;                                          \
                                                          \
    out_m = __msa_maxi_s_w((v4i32) in, 0);                \
    out_m = __msa_min_s_w((v4i32) max_m, (v4i32) out_m);  \
    out_m;                                                \
} )

1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109
#define CLIP_SW_0_255_MAX_SATU(in)                    \
( {                                                   \
    v4i32 out_m;                                      \
                                                      \
    out_m = __msa_maxi_s_w((v4i32) in, 0);            \
    out_m = (v4i32) __msa_sat_u_w((v4u32) out_m, 7);  \
    out_m;                                            \
} )
#define CLIP_SW2_0_255_MAX_SATU(in0, in1)  \
{                                          \
    in0 = CLIP_SW_0_255_MAX_SATU(in0);     \
    in1 = CLIP_SW_0_255_MAX_SATU(in1);     \
}
#define CLIP_SW4_0_255_MAX_SATU(in0, in1, in2, in3)  \
{                                                    \
    CLIP_SW2_0_255_MAX_SATU(in0, in1);               \
    CLIP_SW2_0_255_MAX_SATU(in2, in3);               \
}

1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123
/* Description : Addition of 4 signed word elements
                 4 signed word elements of input vector are added together and
                 resulted integer sum is returned
   Arguments   : Inputs  - in       (signed word vector)
                 Outputs - sum_m    (i32 sum)
                 Return Type - signed word
*/
#define HADD_SW_S32(in)                               \
( {                                                   \
    v2i64 res0_m, res1_m;                             \
    int32_t sum_m;                                    \
                                                      \
    res0_m = __msa_hadd_s_d((v4i32) in, (v4i32) in);  \
    res1_m = __msa_splati_d(res0_m, 1);               \
1124
    res0_m += res1_m;                                 \
1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
    sum_m = __msa_copy_s_w((v4i32) res0_m, 0);        \
    sum_m;                                            \
} )

/* Description : Addition of 8 unsigned halfword elements
                 8 unsigned halfword elements of input vector are added
                 together and resulted integer sum is returned
   Arguments   : Inputs  - in       (unsigned halfword vector)
                 Outputs - sum_m    (u32 sum)
                 Return Type - unsigned word
*/
#define HADD_UH_U32(in)                                  \
( {                                                      \
    v4u32 res_m;                                         \
    v2u64 res0_m, res1_m;                                \
    uint32_t sum_m;                                      \
                                                         \
    res_m = __msa_hadd_u_w((v8u16) in, (v8u16) in);      \
    res0_m = __msa_hadd_u_d(res_m, res_m);               \
    res1_m = (v2u64) __msa_splati_d((v2i64) res0_m, 1);  \
1145
    res0_m += res1_m;                                    \
1146 1147 1148 1149
    sum_m = __msa_copy_u_w((v4i32) res0_m, 0);           \
    sum_m;                                               \
} )

1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172
/* Description : Horizontal addition of signed byte vector elements
   Arguments   : Inputs  - in0, in1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Each signed odd byte element from 'in0' is added to
                 even signed byte element from 'in0' (pairwise) and the
                 halfword result is stored in 'out0'
*/
#define HADD_SB2(RTYPE, in0, in1, out0, out1)                 \
{                                                             \
    out0 = (RTYPE) __msa_hadd_s_h((v16i8) in0, (v16i8) in0);  \
    out1 = (RTYPE) __msa_hadd_s_h((v16i8) in1, (v16i8) in1);  \
}
#define HADD_SB2_SH(...) HADD_SB2(v8i16, __VA_ARGS__)

#define HADD_SB4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3)  \
{                                                                    \
    HADD_SB2(RTYPE, in0, in1, out0, out1);                           \
    HADD_SB2(RTYPE, in2, in3, out2, out3);                           \
}
#define HADD_SB4_UH(...) HADD_SB4(v8u16, __VA_ARGS__)
#define HADD_SB4_SH(...) HADD_SB4(v8i16, __VA_ARGS__)

1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187
/* Description : Horizontal addition of unsigned byte vector elements
   Arguments   : Inputs  - in0, in1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Each unsigned odd byte element from 'in0' is added to
                 even unsigned byte element from 'in0' (pairwise) and the
                 halfword result is stored in 'out0'
*/
#define HADD_UB2(RTYPE, in0, in1, out0, out1)                 \
{                                                             \
    out0 = (RTYPE) __msa_hadd_u_h((v16u8) in0, (v16u8) in0);  \
    out1 = (RTYPE) __msa_hadd_u_h((v16u8) in1, (v16u8) in1);  \
}
#define HADD_UB2_UH(...) HADD_UB2(v8u16, __VA_ARGS__)

1188 1189 1190 1191 1192 1193 1194
#define HADD_UB3(RTYPE, in0, in1, in2, out0, out1, out2)      \
{                                                             \
    HADD_UB2(RTYPE, in0, in1, out0, out1);                    \
    out2 = (RTYPE) __msa_hadd_u_h((v16u8) in2, (v16u8) in2);  \
}
#define HADD_UB3_UH(...) HADD_UB3(v8u16, __VA_ARGS__)

1195 1196 1197 1198 1199 1200 1201 1202 1203
#define HADD_UB4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3)  \
{                                                                    \
    HADD_UB2(RTYPE, in0, in1, out0, out1);                           \
    HADD_UB2(RTYPE, in2, in3, out2, out3);                           \
}
#define HADD_UB4_UB(...) HADD_UB4(v16u8, __VA_ARGS__)
#define HADD_UB4_UH(...) HADD_UB4(v8u16, __VA_ARGS__)
#define HADD_UB4_SH(...) HADD_UB4(v8i16, __VA_ARGS__)

1204 1205 1206 1207 1208 1209 1210 1211 1212
/* Description : Horizontal subtraction of unsigned byte vector elements
   Arguments   : Inputs  - in0, in1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Each unsigned odd byte element from 'in0' is subtracted from
                 even unsigned byte element from 'in0' (pairwise) and the
                 halfword result is stored in 'out0'
*/
#define HSUB_UB2(RTYPE, in0, in1, out0, out1)                 \
1213
{                                                             \
1214 1215 1216 1217 1218 1219
    out0 = (RTYPE) __msa_hsub_u_h((v16u8) in0, (v16u8) in0);  \
    out1 = (RTYPE) __msa_hsub_u_h((v16u8) in1, (v16u8) in1);  \
}
#define HSUB_UB2_UH(...) HSUB_UB2(v8u16, __VA_ARGS__)
#define HSUB_UB2_SH(...) HSUB_UB2(v8i16, __VA_ARGS__)

1220 1221 1222 1223 1224 1225 1226 1227
#define HSUB_UB4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3)  \
{                                                                    \
    HSUB_UB2(RTYPE, in0, in1, out0, out1);                           \
    HSUB_UB2(RTYPE, in2, in3, out2, out3);                           \
}
#define HSUB_UB4_UH(...) HSUB_UB4(v8u16, __VA_ARGS__)
#define HSUB_UB4_SH(...) HSUB_UB4(v8i16, __VA_ARGS__)

1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250
/* Description : SAD (Sum of Absolute Difference)
   Arguments   : Inputs  - in0, in1, ref0, ref1  (unsigned byte src & ref)
                 Outputs - sad_m                 (halfword vector with sad)
                 Return Type - unsigned halfword
   Details     : Absolute difference of all the byte elements from 'in0' with
                 'ref0' is calculated and preserved in 'diff0'. From the 16
                 unsigned absolute diff values, even-odd pairs are added
                 together to generate 8 halfword results.
*/
#define SAD_UB2_UH(in0, in1, ref0, ref1)                        \
( {                                                             \
    v16u8 diff0_m, diff1_m;                                     \
    v8u16 sad_m = { 0 };                                        \
                                                                \
    diff0_m = __msa_asub_u_b((v16u8) in0, (v16u8) ref0);        \
    diff1_m = __msa_asub_u_b((v16u8) in1, (v16u8) ref1);        \
                                                                \
    sad_m += __msa_hadd_u_h((v16u8) diff0_m, (v16u8) diff0_m);  \
    sad_m += __msa_hadd_u_h((v16u8) diff1_m, (v16u8) diff1_m);  \
                                                                \
    sad_m;                                                      \
} )

1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264
/* Description : Insert specified word elements from input vectors to 1
                 destination vector
   Arguments   : Inputs  - in0, in1, in2, in3 (4 input vectors)
                 Outputs - out                (output vector)
                 Return Type - as per RTYPE
*/
#define INSERT_W2(RTYPE, in0, in1, out)                 \
{                                                       \
    out = (RTYPE) __msa_insert_w((v4i32) out, 0, in0);  \
    out = (RTYPE) __msa_insert_w((v4i32) out, 1, in1);  \
}
#define INSERT_W2_UB(...) INSERT_W2(v16u8, __VA_ARGS__)
#define INSERT_W2_SB(...) INSERT_W2(v16i8, __VA_ARGS__)

1265 1266 1267 1268 1269 1270 1271 1272 1273
#define INSERT_W4(RTYPE, in0, in1, in2, in3, out)       \
{                                                       \
    out = (RTYPE) __msa_insert_w((v4i32) out, 0, in0);  \
    out = (RTYPE) __msa_insert_w((v4i32) out, 1, in1);  \
    out = (RTYPE) __msa_insert_w((v4i32) out, 2, in2);  \
    out = (RTYPE) __msa_insert_w((v4i32) out, 3, in3);  \
}
#define INSERT_W4_UB(...) INSERT_W4(v16u8, __VA_ARGS__)
#define INSERT_W4_SB(...) INSERT_W4(v16i8, __VA_ARGS__)
1274
#define INSERT_W4_SH(...) INSERT_W4(v8i16, __VA_ARGS__)
1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289
#define INSERT_W4_SW(...) INSERT_W4(v4i32, __VA_ARGS__)

/* Description : Insert specified double word elements from input vectors to 1
                 destination vector
   Arguments   : Inputs  - in0, in1      (2 input vectors)
                 Outputs - out           (output vector)
                 Return Type - as per RTYPE
*/
#define INSERT_D2(RTYPE, in0, in1, out)                 \
{                                                       \
    out = (RTYPE) __msa_insert_d((v2i64) out, 0, in0);  \
    out = (RTYPE) __msa_insert_d((v2i64) out, 1, in1);  \
}
#define INSERT_D2_UB(...) INSERT_D2(v16u8, __VA_ARGS__)
#define INSERT_D2_SB(...) INSERT_D2(v16i8, __VA_ARGS__)
1290
#define INSERT_D2_SH(...) INSERT_D2(v8i16, __VA_ARGS__)
1291 1292
#define INSERT_D2_SD(...) INSERT_D2(v2i64, __VA_ARGS__)

1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
/* Description : Interleave even byte elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Even byte elements of 'in0' and even byte
                 elements of 'in1' are interleaved and copied to 'out0'
                 Even byte elements of 'in2' and even byte
                 elements of 'in3' are interleaved and copied to 'out1'
*/
#define ILVEV_B2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                            \
    out0 = (RTYPE) __msa_ilvev_b((v16i8) in1, (v16i8) in0);  \
    out1 = (RTYPE) __msa_ilvev_b((v16i8) in3, (v16i8) in2);  \
}
#define ILVEV_B2_UB(...) ILVEV_B2(v16u8, __VA_ARGS__)
#define ILVEV_B2_SB(...) ILVEV_B2(v16i8, __VA_ARGS__)
#define ILVEV_B2_SH(...) ILVEV_B2(v8i16, __VA_ARGS__)
#define ILVEV_B2_SD(...) ILVEV_B2(v2i64, __VA_ARGS__)

1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
/* Description : Interleave even halfword elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Even halfword elements of 'in0' and even halfword
                 elements of 'in1' are interleaved and copied to 'out0'
                 Even halfword elements of 'in2' and even halfword
                 elements of 'in3' are interleaved and copied to 'out1'
*/
#define ILVEV_H2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                            \
    out0 = (RTYPE) __msa_ilvev_h((v8i16) in1, (v8i16) in0);  \
    out1 = (RTYPE) __msa_ilvev_h((v8i16) in3, (v8i16) in2);  \
}
#define ILVEV_H2_UB(...) ILVEV_H2(v16u8, __VA_ARGS__)
1327 1328
#define ILVEV_H2_SH(...) ILVEV_H2(v8i16, __VA_ARGS__)
#define ILVEV_H2_SW(...) ILVEV_H2(v4i32, __VA_ARGS__)
1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343

/* Description : Interleave even word elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Even word elements of 'in0' and even word
                 elements of 'in1' are interleaved and copied to 'out0'
                 Even word elements of 'in2' and even word
                 elements of 'in3' are interleaved and copied to 'out1'
*/
#define ILVEV_W2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                            \
    out0 = (RTYPE) __msa_ilvev_w((v4i32) in1, (v4i32) in0);  \
    out1 = (RTYPE) __msa_ilvev_w((v4i32) in3, (v4i32) in2);  \
}
1344
#define ILVEV_W2_UB(...) ILVEV_W2(v16u8, __VA_ARGS__)
1345
#define ILVEV_W2_SB(...) ILVEV_W2(v16i8, __VA_ARGS__)
1346 1347
#define ILVEV_W2_UH(...) ILVEV_W2(v8u16, __VA_ARGS__)
#define ILVEV_W2_SD(...) ILVEV_W2(v2i64, __VA_ARGS__)
1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363

/* Description : Interleave even double word elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Even double word elements of 'in0' and even double word
                 elements of 'in1' are interleaved and copied to 'out0'
                 Even double word elements of 'in2' and even double word
                 elements of 'in3' are interleaved and copied to 'out1'
*/
#define ILVEV_D2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                            \
    out0 = (RTYPE) __msa_ilvev_d((v2i64) in1, (v2i64) in0);  \
    out1 = (RTYPE) __msa_ilvev_d((v2i64) in3, (v2i64) in2);  \
}
#define ILVEV_D2_UB(...) ILVEV_D2(v16u8, __VA_ARGS__)
1364 1365
#define ILVEV_D2_SB(...) ILVEV_D2(v16i8, __VA_ARGS__)
#define ILVEV_D2_SW(...) ILVEV_D2(v4i32, __VA_ARGS__)
1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379

/* Description : Interleave left half of byte elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Left half of byte elements of in0 and left half of byte
                 elements of in1 are interleaved and copied to out0.
                 Left half of byte elements of in2 and left half of byte
                 elements of in3 are interleaved and copied to out1.
*/
#define ILVL_B2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                           \
    out0 = (RTYPE) __msa_ilvl_b((v16i8) in0, (v16i8) in1);  \
    out1 = (RTYPE) __msa_ilvl_b((v16i8) in2, (v16i8) in3);  \
1380
}
1381
#define ILVL_B2_UB(...) ILVL_B2(v16u8, __VA_ARGS__)
1382
#define ILVL_B2_SB(...) ILVL_B2(v16i8, __VA_ARGS__)
1383
#define ILVL_B2_UH(...) ILVL_B2(v8u16, __VA_ARGS__)
1384
#define ILVL_B2_SH(...) ILVL_B2(v8i16, __VA_ARGS__)
1385

1386 1387
#define ILVL_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                out0, out1, out2, out3)                         \
1388
{                                                               \
1389 1390 1391
    ILVL_B2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    ILVL_B2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
1392
#define ILVL_B4_UB(...) ILVL_B4(v16u8, __VA_ARGS__)
1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409
#define ILVL_B4_SB(...) ILVL_B4(v16i8, __VA_ARGS__)
#define ILVL_B4_UH(...) ILVL_B4(v8u16, __VA_ARGS__)
#define ILVL_B4_SH(...) ILVL_B4(v8i16, __VA_ARGS__)

/* Description : Interleave left half of halfword elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Left half of halfword elements of in0 and left half of halfword
                 elements of in1 are interleaved and copied to out0.
                 Left half of halfword elements of in2 and left half of halfword
                 elements of in3 are interleaved and copied to out1.
*/
#define ILVL_H2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                           \
    out0 = (RTYPE) __msa_ilvl_h((v8i16) in0, (v8i16) in1);  \
    out1 = (RTYPE) __msa_ilvl_h((v8i16) in2, (v8i16) in3);  \
1410
}
1411
#define ILVL_H2_SH(...) ILVL_H2(v8i16, __VA_ARGS__)
1412
#define ILVL_H2_SW(...) ILVL_H2(v4i32, __VA_ARGS__)
1413

1414 1415
#define ILVL_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                out0, out1, out2, out3)                         \
1416
{                                                               \
1417 1418 1419 1420
    ILVL_H2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    ILVL_H2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
#define ILVL_H4_SH(...) ILVL_H4(v8i16, __VA_ARGS__)
1421
#define ILVL_H4_SW(...) ILVL_H4(v4i32, __VA_ARGS__)
1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436

/* Description : Interleave left half of word elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Left half of word elements of in0 and left half of word
                 elements of in1 are interleaved and copied to out0.
                 Left half of word elements of in2 and left half of word
                 elements of in3 are interleaved and copied to out1.
*/
#define ILVL_W2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                           \
    out0 = (RTYPE) __msa_ilvl_w((v4i32) in0, (v4i32) in1);  \
    out1 = (RTYPE) __msa_ilvl_w((v4i32) in2, (v4i32) in3);  \
}
1437
#define ILVL_W2_UB(...) ILVL_W2(v16u8, __VA_ARGS__)
1438
#define ILVL_W2_SB(...) ILVL_W2(v16i8, __VA_ARGS__)
1439
#define ILVL_W2_SH(...) ILVL_W2(v8i16, __VA_ARGS__)
1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454

/* Description : Interleave right half of byte elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7
                 Outputs - out0, out1, out2, out3
                 Return Type - as per RTYPE
   Details     : Right half of byte elements of in0 and right half of byte
                 elements of in1 are interleaved and copied to out0.
                 Right half of byte elements of in2 and right half of byte
                 elements of in3 are interleaved and copied to out1.
                 Similar for other pairs
*/
#define ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                           \
    out0 = (RTYPE) __msa_ilvr_b((v16i8) in0, (v16i8) in1);  \
    out1 = (RTYPE) __msa_ilvr_b((v16i8) in2, (v16i8) in3);  \
1455
}
1456 1457 1458 1459
#define ILVR_B2_UB(...) ILVR_B2(v16u8, __VA_ARGS__)
#define ILVR_B2_SB(...) ILVR_B2(v16i8, __VA_ARGS__)
#define ILVR_B2_UH(...) ILVR_B2(v8u16, __VA_ARGS__)
#define ILVR_B2_SH(...) ILVR_B2(v8i16, __VA_ARGS__)
1460 1461 1462 1463 1464 1465 1466 1467
#define ILVR_B2_SW(...) ILVR_B2(v4i32, __VA_ARGS__)

#define ILVR_B3(RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2)  \
{                                                                       \
    ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1);                     \
    out2 = (RTYPE) __msa_ilvr_b((v16i8) in4, (v16i8) in5);              \
}
#define ILVR_B3_UB(...) ILVR_B3(v16u8, __VA_ARGS__)
1468
#define ILVR_B3_SB(...) ILVR_B3(v16i8, __VA_ARGS__)
1469 1470
#define ILVR_B3_UH(...) ILVR_B3(v8u16, __VA_ARGS__)
#define ILVR_B3_SH(...) ILVR_B3(v8i16, __VA_ARGS__)
1471

1472 1473
#define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                out0, out1, out2, out3)                         \
1474
{                                                               \
1475 1476 1477
    ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    ILVR_B2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
1478
#define ILVR_B4_UB(...) ILVR_B4(v16u8, __VA_ARGS__)
1479 1480 1481
#define ILVR_B4_SB(...) ILVR_B4(v16i8, __VA_ARGS__)
#define ILVR_B4_UH(...) ILVR_B4(v8u16, __VA_ARGS__)
#define ILVR_B4_SH(...) ILVR_B4(v8i16, __VA_ARGS__)
1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
#define ILVR_B4_SW(...) ILVR_B4(v4i32, __VA_ARGS__)

#define ILVR_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,    \
                in8, in9, in10, in11, in12, in13, in14, in15,     \
                out0, out1, out2, out3, out4, out5, out6, out7)   \
{                                                                 \
    ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,        \
            out0, out1, out2, out3);                              \
    ILVR_B4(RTYPE, in8, in9, in10, in11, in12, in13, in14, in15,  \
            out4, out5, out6, out7);                              \
}
#define ILVR_B8_UH(...) ILVR_B8(v8u16, __VA_ARGS__)
1494 1495 1496 1497

/* Description : Interleave right half of halfword elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7
                 Outputs - out0, out1, out2, out3
1498
                 Return Type - as per RTYPE
1499 1500 1501 1502 1503 1504 1505
   Details     : Right half of halfword elements of in0 and right half of
                 halfword elements of in1 are interleaved and copied to out0.
                 Right half of halfword elements of in2 and right half of
                 halfword elements of in3 are interleaved and copied to out1.
                 Similar for other pairs
*/
#define ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1)      \
1506
{                                                           \
1507 1508
    out0 = (RTYPE) __msa_ilvr_h((v8i16) in0, (v8i16) in1);  \
    out1 = (RTYPE) __msa_ilvr_h((v8i16) in2, (v8i16) in3);  \
1509
}
1510
#define ILVR_H2_SH(...) ILVR_H2(v8i16, __VA_ARGS__)
1511
#define ILVR_H2_SW(...) ILVR_H2(v4i32, __VA_ARGS__)
1512

1513 1514 1515 1516
#define ILVR_H3(RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2)  \
{                                                                       \
    ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1);                     \
    out2 = (RTYPE) __msa_ilvr_h((v8i16) in4, (v8i16) in5);              \
1517
}
1518
#define ILVR_H3_SH(...) ILVR_H3(v8i16, __VA_ARGS__)
1519

1520 1521 1522 1523 1524
#define ILVR_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                out0, out1, out2, out3)                         \
{                                                               \
    ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    ILVR_H2(RTYPE, in4, in5, in6, in7, out2, out3);             \
1525
}
1526
#define ILVR_H4_SH(...) ILVR_H4(v8i16, __VA_ARGS__)
1527
#define ILVR_H4_SW(...) ILVR_H4(v4i32, __VA_ARGS__)
1528

1529 1530 1531 1532
#define ILVR_W2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                           \
    out0 = (RTYPE) __msa_ilvr_w((v4i32) in0, (v4i32) in1);  \
    out1 = (RTYPE) __msa_ilvr_w((v4i32) in2, (v4i32) in3);  \
1533
}
1534 1535
#define ILVR_W2_UB(...) ILVR_W2(v16u8, __VA_ARGS__)
#define ILVR_W2_SB(...) ILVR_W2(v16i8, __VA_ARGS__)
1536
#define ILVR_W2_SH(...) ILVR_W2(v8i16, __VA_ARGS__)
1537

1538 1539 1540 1541 1542 1543 1544
#define ILVR_W4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                out0, out1, out2, out3)                         \
{                                                               \
    ILVR_W2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    ILVR_W2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
#define ILVR_W4_SB(...) ILVR_W4(v16i8, __VA_ARGS__)
1545
#define ILVR_W4_UB(...) ILVR_W4(v16u8, __VA_ARGS__)
1546 1547 1548 1549

/* Description : Interleave right half of double word elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7
                 Outputs - out0, out1, out2, out3
1550
                 Return Type - as per RTYPE
1551 1552 1553 1554 1555
   Details     : Right half of double word elements of in0 and right half of
                 double word elements of in1 are interleaved and copied to out0.
                 Right half of double word elements of in2 and right half of
                 double word elements of in3 are interleaved and copied to out1.
*/
1556 1557 1558 1559
#define ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                           \
    out0 = (RTYPE) __msa_ilvr_d((v2i64) in0, (v2i64) in1);  \
    out1 = (RTYPE) __msa_ilvr_d((v2i64) in2, (v2i64) in3);  \
1560
}
1561
#define ILVR_D2_UB(...) ILVR_D2(v16u8, __VA_ARGS__)
1562 1563
#define ILVR_D2_SB(...) ILVR_D2(v16i8, __VA_ARGS__)
#define ILVR_D2_SH(...) ILVR_D2(v8i16, __VA_ARGS__)
1564

1565 1566 1567
#define ILVR_D3(RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2)  \
{                                                                       \
    ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1);                     \
1568
    out2 = (RTYPE) __msa_ilvr_d((v2i64) in4, (v2i64) in5);              \
1569
}
1570
#define ILVR_D3_SB(...) ILVR_D3(v16i8, __VA_ARGS__)
1571

1572 1573 1574 1575 1576 1577 1578
#define ILVR_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                out0, out1, out2, out3)                         \
{                                                               \
    ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    ILVR_D2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
#define ILVR_D4_SB(...) ILVR_D4(v16i8, __VA_ARGS__)
1579
#define ILVR_D4_UB(...) ILVR_D4(v16u8, __VA_ARGS__)
1580

1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598
/* Description : Interleave left half of double word elements from vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Left half of double word elements of in0 and left half of
                 double word elements of in1 are interleaved and copied to out0.
                 Left half of double word elements of in2 and left half of
                 double word elements of in3 are interleaved and copied to out1.
*/
#define ILVL_D2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                           \
    out0 = (RTYPE) __msa_ilvl_d((v2i64) in0, (v2i64) in1);  \
    out1 = (RTYPE) __msa_ilvl_d((v2i64) in2, (v2i64) in3);  \
}
#define ILVL_D2_UB(...) ILVL_D2(v16u8, __VA_ARGS__)
#define ILVL_D2_SB(...) ILVL_D2(v16i8, __VA_ARGS__)
#define ILVL_D2_SH(...) ILVL_D2(v8i16, __VA_ARGS__)

1599 1600 1601 1602 1603 1604 1605 1606 1607 1608
/* Description : Interleave both left and right half of input vectors
   Arguments   : Inputs  - in0, in1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Right half of byte elements from 'in0' and 'in1' are
                 interleaved and stored to 'out0'
                 Left half of byte elements from 'in0' and 'in1' are
                 interleaved and stored to 'out1'
*/
#define ILVRL_B2(RTYPE, in0, in1, out0, out1)               \
1609
{                                                           \
1610 1611
    out0 = (RTYPE) __msa_ilvr_b((v16i8) in0, (v16i8) in1);  \
    out1 = (RTYPE) __msa_ilvl_b((v16i8) in0, (v16i8) in1);  \
1612
}
1613
#define ILVRL_B2_UB(...) ILVRL_B2(v16u8, __VA_ARGS__)
1614
#define ILVRL_B2_SB(...) ILVRL_B2(v16i8, __VA_ARGS__)
1615
#define ILVRL_B2_UH(...) ILVRL_B2(v8u16, __VA_ARGS__)
1616
#define ILVRL_B2_SH(...) ILVRL_B2(v8i16, __VA_ARGS__)
1617
#define ILVRL_B2_SW(...) ILVRL_B2(v4i32, __VA_ARGS__)
1618

1619
#define ILVRL_H2(RTYPE, in0, in1, out0, out1)               \
1620
{                                                           \
1621 1622
    out0 = (RTYPE) __msa_ilvr_h((v8i16) in0, (v8i16) in1);  \
    out1 = (RTYPE) __msa_ilvl_h((v8i16) in0, (v8i16) in1);  \
1623
}
1624
#define ILVRL_H2_UB(...) ILVRL_H2(v16u8, __VA_ARGS__)
1625 1626 1627
#define ILVRL_H2_SB(...) ILVRL_H2(v16i8, __VA_ARGS__)
#define ILVRL_H2_SH(...) ILVRL_H2(v8i16, __VA_ARGS__)
#define ILVRL_H2_SW(...) ILVRL_H2(v4i32, __VA_ARGS__)
1628

1629
#define ILVRL_W2(RTYPE, in0, in1, out0, out1)               \
1630
{                                                           \
1631 1632 1633
    out0 = (RTYPE) __msa_ilvr_w((v4i32) in0, (v4i32) in1);  \
    out1 = (RTYPE) __msa_ilvl_w((v4i32) in0, (v4i32) in1);  \
}
1634
#define ILVRL_W2_UB(...) ILVRL_W2(v16u8, __VA_ARGS__)
1635
#define ILVRL_W2_SH(...) ILVRL_W2(v8i16, __VA_ARGS__)
1636
#define ILVRL_W2_SW(...) ILVRL_W2(v4i32, __VA_ARGS__)
1637 1638 1639 1640 1641

/* Description : Maximum values between signed elements of vector and
                 5-bit signed immediate value are copied to the output vector
   Arguments   : Inputs  - in0, in1, in2, in3, max_val
                 Outputs - in0, in1, in2, in3 (in place)
1642
                 Return Type - as per RTYPE
1643 1644 1645
   Details     : Maximum of signed halfword element values from 'in0' and
                 'max_val' are written to output vector 'in0'
*/
1646 1647 1648 1649
#define MAXI_SH2(RTYPE, in0, in1, max_val)               \
{                                                        \
    in0 = (RTYPE) __msa_maxi_s_h((v8i16) in0, max_val);  \
    in1 = (RTYPE) __msa_maxi_s_h((v8i16) in1, max_val);  \
1650
}
1651
#define MAXI_SH2_UH(...) MAXI_SH2(v8u16, __VA_ARGS__)
1652 1653 1654 1655 1656 1657 1658 1659
#define MAXI_SH2_SH(...) MAXI_SH2(v8i16, __VA_ARGS__)

#define MAXI_SH4(RTYPE, in0, in1, in2, in3, max_val)  \
{                                                     \
    MAXI_SH2(RTYPE, in0, in1, max_val);               \
    MAXI_SH2(RTYPE, in2, in3, max_val);               \
}
#define MAXI_SH4_UH(...) MAXI_SH4(v8u16, __VA_ARGS__)
1660 1661 1662 1663 1664 1665 1666 1667 1668
#define MAXI_SH4_SH(...) MAXI_SH4(v8i16, __VA_ARGS__)

#define MAXI_SH8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, max_val)  \
{                                                                         \
    MAXI_SH4(RTYPE, in0, in1, in2, in3, max_val);                         \
    MAXI_SH4(RTYPE, in4, in5, in6, in7, max_val);                         \
}
#define MAXI_SH8_UH(...) MAXI_SH8(v8u16, __VA_ARGS__)
#define MAXI_SH8_SH(...) MAXI_SH8(v8i16, __VA_ARGS__)
1669 1670 1671 1672 1673 1674

/* Description : Saturate the halfword element values to the max
                 unsigned value of (sat_val+1 bits)
                 The element data width remains unchanged
   Arguments   : Inputs  - in0, in1, in2, in3, sat_val
                 Outputs - in0, in1, in2, in3 (in place)
1675
                 Return Type - as per RTYPE
1676 1677 1678 1679 1680 1681 1682 1683
   Details     : Each unsigned halfword element from 'in0' is saturated to the
                 value generated with (sat_val+1) bit range
                 Results are in placed to original vectors
*/
#define SAT_UH2(RTYPE, in0, in1, sat_val)               \
{                                                       \
    in0 = (RTYPE) __msa_sat_u_h((v8u16) in0, sat_val);  \
    in1 = (RTYPE) __msa_sat_u_h((v8u16) in1, sat_val);  \
1684
}
1685
#define SAT_UH2_UH(...) SAT_UH2(v8u16, __VA_ARGS__)
1686
#define SAT_UH2_SH(...) SAT_UH2(v8i16, __VA_ARGS__)
1687

1688
#define SAT_UH4(RTYPE, in0, in1, in2, in3, sat_val)  \
1689
{                                                    \
1690
    SAT_UH2(RTYPE, in0, in1, sat_val);               \
1691
    SAT_UH2(RTYPE, in2, in3, sat_val);               \
1692 1693
}
#define SAT_UH4_UH(...) SAT_UH4(v8u16, __VA_ARGS__)
1694 1695 1696 1697 1698 1699 1700 1701 1702
#define SAT_UH4_SH(...) SAT_UH4(v8i16, __VA_ARGS__)

#define SAT_UH8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, sat_val)  \
{                                                                        \
    SAT_UH4(RTYPE, in0, in1, in2, in3, sat_val);                         \
    SAT_UH4(RTYPE, in4, in5, in6, in7, sat_val);                         \
}
#define SAT_UH8_UH(...) SAT_UH8(v8u16, __VA_ARGS__)
#define SAT_UH8_SH(...) SAT_UH8(v8i16, __VA_ARGS__)
1703

1704 1705 1706 1707 1708
/* Description : Saturate the halfword element values to the max
                 unsigned value of (sat_val+1 bits)
                 The element data width remains unchanged
   Arguments   : Inputs  - in0, in1, in2, in3, sat_val
                 Outputs - in0, in1, in2, in3 (in place)
1709
                 Return Type - as per RTYPE
1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722
   Details     : Each unsigned halfword element from 'in0' is saturated to the
                 value generated with (sat_val+1) bit range
                 Results are in placed to original vectors
*/
#define SAT_SH2(RTYPE, in0, in1, sat_val)               \
{                                                       \
    in0 = (RTYPE) __msa_sat_s_h((v8i16) in0, sat_val);  \
    in1 = (RTYPE) __msa_sat_s_h((v8i16) in1, sat_val);  \
}
#define SAT_SH2_SH(...) SAT_SH2(v8i16, __VA_ARGS__)

#define SAT_SH3(RTYPE, in0, in1, in2, sat_val)          \
{                                                       \
1723
    SAT_SH2(RTYPE, in0, in1, sat_val);                  \
1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734
    in2 = (RTYPE) __msa_sat_s_h((v8i16) in2, sat_val);  \
}
#define SAT_SH3_SH(...) SAT_SH3(v8i16, __VA_ARGS__)

#define SAT_SH4(RTYPE, in0, in1, in2, in3, sat_val)  \
{                                                    \
    SAT_SH2(RTYPE, in0, in1, sat_val);               \
    SAT_SH2(RTYPE, in2, in3, sat_val);               \
}
#define SAT_SH4_SH(...) SAT_SH4(v8i16, __VA_ARGS__)

1735 1736 1737 1738 1739
/* Description : Saturate the word element values to the max
                 unsigned value of (sat_val+1 bits)
                 The element data width remains unchanged
   Arguments   : Inputs  - in0, in1, in2, in3, sat_val
                 Outputs - in0, in1, in2, in3 (in place)
1740
                 Return Type - as per RTYPE
1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758
   Details     : Each unsigned word element from 'in0' is saturated to the
                 value generated with (sat_val+1) bit range
                 Results are in placed to original vectors
*/
#define SAT_SW2(RTYPE, in0, in1, sat_val)               \
{                                                       \
    in0 = (RTYPE) __msa_sat_s_w((v4i32) in0, sat_val);  \
    in1 = (RTYPE) __msa_sat_s_w((v4i32) in1, sat_val);  \
}
#define SAT_SW2_SW(...) SAT_SW2(v4i32, __VA_ARGS__)

#define SAT_SW4(RTYPE, in0, in1, in2, in3, sat_val)  \
{                                                    \
    SAT_SW2(RTYPE, in0, in1, sat_val);               \
    SAT_SW2(RTYPE, in2, in3, sat_val);               \
}
#define SAT_SW4_SW(...) SAT_SW4(v4i32, __VA_ARGS__)

1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772
/* Description : Indexed halfword element values are replicated to all
                 elements in output vector
   Arguments   : Inputs  - in, idx0, idx1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : 'idx0' element value from 'in' vector is replicated to all
                  elements in 'out0' vector
                  Valid index range for halfword operation is 0-7
*/
#define SPLATI_H2(RTYPE, in, idx0, idx1, out0, out1)  \
{                                                     \
    out0 = (RTYPE) __msa_splati_h((v8i16) in, idx0);  \
    out1 = (RTYPE) __msa_splati_h((v8i16) in, idx1);  \
}
1773
#define SPLATI_H2_SB(...) SPLATI_H2(v16i8, __VA_ARGS__)
1774 1775
#define SPLATI_H2_SH(...) SPLATI_H2(v8i16, __VA_ARGS__)

1776 1777 1778 1779 1780 1781 1782 1783 1784
#define SPLATI_H3(RTYPE, in, idx0, idx1, idx2,        \
                  out0, out1, out2)                   \
{                                                     \
    SPLATI_H2(RTYPE, in, idx0, idx1, out0, out1);     \
    out2 = (RTYPE) __msa_splati_h((v8i16) in, idx2);  \
}
#define SPLATI_H3_SB(...) SPLATI_H3(v16i8, __VA_ARGS__)
#define SPLATI_H3_SH(...) SPLATI_H3(v8i16, __VA_ARGS__)

1785 1786 1787 1788 1789 1790
#define SPLATI_H4(RTYPE, in, idx0, idx1, idx2, idx3,  \
                  out0, out1, out2, out3)             \
{                                                     \
    SPLATI_H2(RTYPE, in, idx0, idx1, out0, out1);     \
    SPLATI_H2(RTYPE, in, idx2, idx3, out2, out3);     \
}
1791
#define SPLATI_H4_SB(...) SPLATI_H4(v16i8, __VA_ARGS__)
1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809
#define SPLATI_H4_SH(...) SPLATI_H4(v8i16, __VA_ARGS__)

/* Description : Indexed word element values are replicated to all
                 elements in output vector
   Arguments   : Inputs  - in, stidx
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : 'stidx' element value from 'in' vector is replicated to all
                  elements in 'out0' vector
                 'stidx + 1' element value from 'in' vector is replicated to all
                  elements in 'out1' vector
                  Valid index range for halfword operation is 0-3
*/
#define SPLATI_W2(RTYPE, in, stidx, out0, out1)            \
{                                                          \
    out0 = (RTYPE) __msa_splati_w((v4i32) in, stidx);      \
    out1 = (RTYPE) __msa_splati_w((v4i32) in, (stidx+1));  \
}
1810
#define SPLATI_W2_SH(...) SPLATI_W2(v8i16, __VA_ARGS__)
1811 1812 1813 1814 1815 1816 1817
#define SPLATI_W2_SW(...) SPLATI_W2(v4i32, __VA_ARGS__)

#define SPLATI_W4(RTYPE, in, out0, out1, out2, out3)  \
{                                                     \
    SPLATI_W2(RTYPE, in, 0, out0, out1);              \
    SPLATI_W2(RTYPE, in, 2, out2, out3);              \
}
1818
#define SPLATI_W4_SH(...) SPLATI_W4(v8i16, __VA_ARGS__)
1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832
#define SPLATI_W4_SW(...) SPLATI_W4(v4i32, __VA_ARGS__)

/* Description : Pack even byte elements of vector pairs
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Even byte elements of in0 are copied to the left half of
                 out0 & even byte elements of in1 are copied to the right
                 half of out0.
                 Even byte elements of in2 are copied to the left half of
                 out1 & even byte elements of in3 are copied to the right
                 half of out1.
*/
#define PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1)      \
1833
{                                                            \
1834 1835
    out0 = (RTYPE) __msa_pckev_b((v16i8) in0, (v16i8) in1);  \
    out1 = (RTYPE) __msa_pckev_b((v16i8) in2, (v16i8) in3);  \
1836
}
1837 1838 1839 1840
#define PCKEV_B2_SB(...) PCKEV_B2(v16i8, __VA_ARGS__)
#define PCKEV_B2_UB(...) PCKEV_B2(v16u8, __VA_ARGS__)
#define PCKEV_B2_SH(...) PCKEV_B2(v8i16, __VA_ARGS__)
#define PCKEV_B2_SW(...) PCKEV_B2(v4i32, __VA_ARGS__)
1841

1842 1843 1844 1845
#define PCKEV_B3(RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2)  \
{                                                                        \
    PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1);                     \
    out2 = (RTYPE) __msa_pckev_b((v16i8) in4, (v16i8) in5);              \
1846
}
1847
#define PCKEV_B3_UB(...) PCKEV_B3(v16u8, __VA_ARGS__)
1848
#define PCKEV_B3_SB(...) PCKEV_B3(v16i8, __VA_ARGS__)
1849

1850 1851 1852 1853 1854 1855 1856 1857
#define PCKEV_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                 out0, out1, out2, out3)                         \
{                                                                \
    PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    PCKEV_B2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
#define PCKEV_B4_SB(...) PCKEV_B4(v16i8, __VA_ARGS__)
#define PCKEV_B4_UB(...) PCKEV_B4(v16u8, __VA_ARGS__)
1858 1859
#define PCKEV_B4_SH(...) PCKEV_B4(v8i16, __VA_ARGS__)
#define PCKEV_B4_SW(...) PCKEV_B4(v4i32, __VA_ARGS__)
1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872

/* Description : Pack even halfword elements of vector pairs
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Even halfword elements of in0 are copied to the left half of
                 out0 & even halfword elements of in1 are copied to the right
                 half of out0.
                 Even halfword elements of in2 are copied to the left half of
                 out1 & even halfword elements of in3 are copied to the right
                 half of out1.
*/
#define PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1)      \
1873
{                                                            \
1874 1875
    out0 = (RTYPE) __msa_pckev_h((v8i16) in0, (v8i16) in1);  \
    out1 = (RTYPE) __msa_pckev_h((v8i16) in2, (v8i16) in3);  \
1876
}
1877
#define PCKEV_H2_SH(...) PCKEV_H2(v8i16, __VA_ARGS__)
1878
#define PCKEV_H2_SW(...) PCKEV_H2(v4i32, __VA_ARGS__)
1879

1880 1881 1882 1883 1884 1885
#define PCKEV_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                 out0, out1, out2, out3)                         \
{                                                                \
    PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    PCKEV_H2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
1886
#define PCKEV_H4_SH(...) PCKEV_H4(v8i16, __VA_ARGS__)
1887 1888
#define PCKEV_H4_SW(...) PCKEV_H4(v4i32, __VA_ARGS__)

1889 1890 1891
/* Description : Pack even double word elements of vector pairs
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
1892
                 Return Type - as per RTYPE
1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916
   Details     : Even double elements of in0 are copied to the left half of
                 out0 & even double elements of in1 are copied to the right
                 half of out0.
                 Even double elements of in2 are copied to the left half of
                 out1 & even double elements of in3 are copied to the right
                 half of out1.
*/
#define PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                            \
    out0 = (RTYPE) __msa_pckev_d((v2i64) in0, (v2i64) in1);  \
    out1 = (RTYPE) __msa_pckev_d((v2i64) in2, (v2i64) in3);  \
}
#define PCKEV_D2_UB(...) PCKEV_D2(v16u8, __VA_ARGS__)
#define PCKEV_D2_SB(...) PCKEV_D2(v16i8, __VA_ARGS__)
#define PCKEV_D2_SH(...) PCKEV_D2(v8i16, __VA_ARGS__)

#define PCKEV_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                 out0, out1, out2, out3)                         \
{                                                                \
    PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    PCKEV_D2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
#define PCKEV_D4_UB(...) PCKEV_D4(v16u8, __VA_ARGS__)

1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934
/* Description : Pack odd double word elements of vector pairs
   Arguments   : Inputs  - in0, in1
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : As operation is on same input 'in0' vector, index 1 double word
                 element is overwritten to index 0 and result is written to out0
                 As operation is on same input 'in1' vector, index 1 double word
                 element is overwritten to index 0 and result is written to out1
*/
#define PCKOD_D2(RTYPE, in0, in1, in2, in3, out0, out1)      \
{                                                            \
    out0 = (RTYPE) __msa_pckod_d((v2i64) in0, (v2i64) in1);  \
    out1 = (RTYPE) __msa_pckod_d((v2i64) in2, (v2i64) in3);  \
}
#define PCKOD_D2_UB(...) PCKOD_D2(v16u8, __VA_ARGS__)
#define PCKOD_D2_SH(...) PCKOD_D2(v8i16, __VA_ARGS__)
#define PCKOD_D2_SD(...) PCKOD_D2(v2i64, __VA_ARGS__)

1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951
/* Description : Each byte element is logically xor'ed with immediate 128
   Arguments   : Inputs  - in0, in1
                 Outputs - in0, in1 (in-place)
                 Return Type - as per RTYPE
   Details     : Each unsigned byte element from input vector 'in0' is
                 logically xor'ed with 128 and result is in-place stored in
                 'in0' vector
                 Each unsigned byte element from input vector 'in1' is
                 logically xor'ed with 128 and result is in-place stored in
                 'in1' vector
                 Similar for other pairs
*/
#define XORI_B2_128(RTYPE, in0, in1)               \
{                                                  \
    in0 = (RTYPE) __msa_xori_b((v16u8) in0, 128);  \
    in1 = (RTYPE) __msa_xori_b((v16u8) in1, 128);  \
}
1952
#define XORI_B2_128_UB(...) XORI_B2_128(v16u8, __VA_ARGS__)
1953
#define XORI_B2_128_SB(...) XORI_B2_128(v16i8, __VA_ARGS__)
1954
#define XORI_B2_128_SH(...) XORI_B2_128(v8i16, __VA_ARGS__)
1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975

#define XORI_B3_128(RTYPE, in0, in1, in2)          \
{                                                  \
    XORI_B2_128(RTYPE, in0, in1);                  \
    in2 = (RTYPE) __msa_xori_b((v16u8) in2, 128);  \
}
#define XORI_B3_128_SB(...) XORI_B3_128(v16i8, __VA_ARGS__)

#define XORI_B4_128(RTYPE, in0, in1, in2, in3)  \
{                                               \
    XORI_B2_128(RTYPE, in0, in1);               \
    XORI_B2_128(RTYPE, in2, in3);               \
}
#define XORI_B4_128_UB(...) XORI_B4_128(v16u8, __VA_ARGS__)
#define XORI_B4_128_SB(...) XORI_B4_128(v16i8, __VA_ARGS__)
#define XORI_B4_128_SH(...) XORI_B4_128(v8i16, __VA_ARGS__)

#define XORI_B5_128(RTYPE, in0, in1, in2, in3, in4)  \
{                                                    \
    XORI_B3_128(RTYPE, in0, in1, in2);               \
    XORI_B2_128(RTYPE, in3, in4);                    \
1976
}
1977
#define XORI_B5_128_SB(...) XORI_B5_128(v16i8, __VA_ARGS__)
1978

1979 1980 1981 1982 1983 1984 1985
#define XORI_B6_128(RTYPE, in0, in1, in2, in3, in4, in5)  \
{                                                         \
    XORI_B4_128(RTYPE, in0, in1, in2, in3);               \
    XORI_B2_128(RTYPE, in4, in5);                         \
}
#define XORI_B6_128_SB(...) XORI_B6_128(v16i8, __VA_ARGS__)

1986 1987 1988 1989
#define XORI_B7_128(RTYPE, in0, in1, in2, in3, in4, in5, in6)  \
{                                                              \
    XORI_B4_128(RTYPE, in0, in1, in2, in3);                    \
    XORI_B3_128(RTYPE, in4, in5, in6);                         \
1990
}
1991
#define XORI_B7_128_SB(...) XORI_B7_128(v16i8, __VA_ARGS__)
1992

1993 1994 1995 1996 1997 1998
#define XORI_B8_128(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7)  \
{                                                                   \
    XORI_B4_128(RTYPE, in0, in1, in2, in3);                         \
    XORI_B4_128(RTYPE, in4, in5, in6, in7);                         \
}
#define XORI_B8_128_SB(...) XORI_B8_128(v16i8, __VA_ARGS__)
1999
#define XORI_B8_128_UB(...) XORI_B8_128(v16u8, __VA_ARGS__)
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013

/* Description : Addition of signed halfword elements and signed saturation
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
                 Return Type - as per RTYPE
   Details     : Signed halfword elements from 'in0' are added to signed
                 halfword elements of 'in1'. The result is then signed saturated
                 between -32768 to +32767 (as per halfword data type)
                 Similar for other pairs
*/
#define ADDS_SH2(RTYPE, in0, in1, in2, in3, out0, out1)       \
{                                                             \
    out0 = (RTYPE) __msa_adds_s_h((v8i16) in0, (v8i16) in1);  \
    out1 = (RTYPE) __msa_adds_s_h((v8i16) in2, (v8i16) in3);  \
2014
}
2015
#define ADDS_SH2_SH(...) ADDS_SH2(v8i16, __VA_ARGS__)
2016

2017 2018 2019 2020 2021 2022 2023
#define ADDS_SH4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                 out0, out1, out2, out3)                         \
{                                                                \
    ADDS_SH2(RTYPE, in0, in1, in2, in3, out0, out1);             \
    ADDS_SH2(RTYPE, in4, in5, in6, in7, out2, out3);             \
}
#define ADDS_SH4_UH(...) ADDS_SH4(v8u16, __VA_ARGS__)
2024
#define ADDS_SH4_SH(...) ADDS_SH4(v8i16, __VA_ARGS__)
2025 2026 2027 2028 2029 2030 2031 2032 2033

/* Description : Shift left all elements of vector (generic for all data types)
   Arguments   : Inputs  - in0, in1, in2, in3, shift
                 Outputs - in0, in1, in2, in3 (in place)
                 Return Type - as per input vector RTYPE
   Details     : Each element of vector 'in0' is left shifted by 'shift' and
                 result is in place written to 'in0'
                 Similar for other pairs
*/
2034 2035 2036 2037 2038
#define SLLI_2V(in0, in1, shift)  \
{                                 \
    in0 = in0 << shift;           \
    in1 = in1 << shift;           \
}
2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057
#define SLLI_4V(in0, in1, in2, in3, shift)  \
{                                           \
    in0 = in0 << shift;                     \
    in1 = in1 << shift;                     \
    in2 = in2 << shift;                     \
    in3 = in3 << shift;                     \
}

/* Description : Arithmetic shift right all elements of vector
                 (generic for all data types)
   Arguments   : Inputs  - in0, in1, in2, in3, shift
                 Outputs - in0, in1, in2, in3 (in place)
                 Return Type - as per input vector RTYPE
   Details     : Each element of vector 'in0' is right shifted by 'shift' and
                 result is in place written to 'in0'
                 Here, 'shift' is GP variable passed in
                 Similar for other pairs
*/
#define SRA_4V(in0, in1, in2, in3, shift)  \
2058
{                                          \
2059 2060 2061 2062 2063 2064 2065 2066 2067
    in0 = in0 >> shift;                    \
    in1 = in1 >> shift;                    \
    in2 = in2 >> shift;                    \
    in3 = in3 >> shift;                    \
}

/* Description : Shift right logical all halfword elements of vector
   Arguments   : Inputs  - in0, in1, in2, in3, shift
                 Outputs - in0, in1, in2, in3 (in place)
2068
                 Return Type - as per RTYPE
2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083
   Details     : Each element of vector 'in0' is shifted right logical by
                 number of bits respective element holds in vector 'shift' and
                 result is in place written to 'in0'
                 Here, 'shift' is a vector passed in
                 Similar for other pairs
*/
#define SRL_H4(RTYPE, in0, in1, in2, in3, shift)            \
{                                                           \
    in0 = (RTYPE) __msa_srl_h((v8i16) in0, (v8i16) shift);  \
    in1 = (RTYPE) __msa_srl_h((v8i16) in1, (v8i16) shift);  \
    in2 = (RTYPE) __msa_srl_h((v8i16) in2, (v8i16) shift);  \
    in3 = (RTYPE) __msa_srl_h((v8i16) in3, (v8i16) shift);  \
}
#define SRL_H4_UH(...) SRL_H4(v8u16, __VA_ARGS__)

2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101
#define SRLR_H4(RTYPE, in0, in1, in2, in3, shift)            \
{                                                            \
    in0 = (RTYPE) __msa_srlr_h((v8i16) in0, (v8i16) shift);  \
    in1 = (RTYPE) __msa_srlr_h((v8i16) in1, (v8i16) shift);  \
    in2 = (RTYPE) __msa_srlr_h((v8i16) in2, (v8i16) shift);  \
    in3 = (RTYPE) __msa_srlr_h((v8i16) in3, (v8i16) shift);  \
}
#define SRLR_H4_UH(...) SRLR_H4(v8u16, __VA_ARGS__)
#define SRLR_H4_SH(...) SRLR_H4(v8i16, __VA_ARGS__)

#define SRLR_H8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, shift)  \
{                                                                      \
    SRLR_H4(RTYPE, in0, in1, in2, in3, shift);                         \
    SRLR_H4(RTYPE, in4, in5, in6, in7, shift);                         \
}
#define SRLR_H8_UH(...) SRLR_H8(v8u16, __VA_ARGS__)
#define SRLR_H8_SH(...) SRLR_H8(v8i16, __VA_ARGS__)

2102 2103 2104
/* Description : Shift right arithmetic rounded halfwords
   Arguments   : Inputs  - in0, in1, shift
                 Outputs - in0, in1, (in place)
2105
                 Return Type - as per RTYPE
2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134
   Details     : Each element of vector 'in0' is shifted right arithmetic by
                 number of bits respective element holds in vector 'shift'.
                 The last discarded bit is added to shifted value for rounding
                 and the result is in place written to 'in0'
                 Here, 'shift' is a vector passed in
                 Similar for other pairs
*/
#define SRAR_H2(RTYPE, in0, in1, shift)                      \
{                                                            \
    in0 = (RTYPE) __msa_srar_h((v8i16) in0, (v8i16) shift);  \
    in1 = (RTYPE) __msa_srar_h((v8i16) in1, (v8i16) shift);  \
}
#define SRAR_H2_UH(...) SRAR_H2(v8u16, __VA_ARGS__)
#define SRAR_H2_SH(...) SRAR_H2(v8i16, __VA_ARGS__)

#define SRAR_H3(RTYPE, in0, in1, in2, shift)                 \
{                                                            \
    SRAR_H2(RTYPE, in0, in1, shift)                          \
    in2 = (RTYPE) __msa_srar_h((v8i16) in2, (v8i16) shift);  \
}
#define SRAR_H3_SH(...) SRAR_H3(v8i16, __VA_ARGS__)

#define SRAR_H4(RTYPE, in0, in1, in2, in3, shift)  \
{                                                  \
    SRAR_H2(RTYPE, in0, in1, shift)                \
    SRAR_H2(RTYPE, in2, in3, shift)                \
}
#define SRAR_H4_UH(...) SRAR_H4(v8u16, __VA_ARGS__)
#define SRAR_H4_SH(...) SRAR_H4(v8i16, __VA_ARGS__)
2135

2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160
/* Description : Shift right arithmetic rounded words
   Arguments   : Inputs  - in0, in1, shift
                 Outputs - in0, in1, (in place)
                 Return Type - as per RTYPE
   Details     : Each element of vector 'in0' is shifted right arithmetic by
                 number of bits respective element holds in vector 'shift'.
                 The last discarded bit is added to shifted value for rounding
                 and the result is in place written to 'in0'
                 Here, 'shift' is a vector passed in
                 Similar for other pairs
*/
#define SRAR_W2(RTYPE, in0, in1, shift)                      \
{                                                            \
    in0 = (RTYPE) __msa_srar_w((v4i32) in0, (v4i32) shift);  \
    in1 = (RTYPE) __msa_srar_w((v4i32) in1, (v4i32) shift);  \
}
#define SRAR_W2_SW(...) SRAR_W2(v4i32, __VA_ARGS__)

#define SRAR_W4(RTYPE, in0, in1, in2, in3, shift)  \
{                                                  \
    SRAR_W2(RTYPE, in0, in1, shift)                \
    SRAR_W2(RTYPE, in2, in3, shift)                \
}
#define SRAR_W4_SW(...) SRAR_W4(v4i32, __VA_ARGS__)

2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178
/* Description : Shift right arithmetic rounded (immediate)
   Arguments   : Inputs  - in0, in1, in2, in3, shift
                 Outputs - in0, in1, in2, in3 (in place)
                 Return Type - as per RTYPE
   Details     : Each element of vector 'in0' is shifted right arithmetic by
                 value in 'shift'.
                 The last discarded bit is added to shifted value for rounding
                 and the result is in place written to 'in0'
                 Similar for other pairs
*/
#define SRARI_H2(RTYPE, in0, in1, shift)              \
{                                                     \
    in0 = (RTYPE) __msa_srari_h((v8i16) in0, shift);  \
    in1 = (RTYPE) __msa_srari_h((v8i16) in1, shift);  \
}
#define SRARI_H2_UH(...) SRARI_H2(v8u16, __VA_ARGS__)
#define SRARI_H2_SH(...) SRARI_H2(v8i16, __VA_ARGS__)

2179 2180 2181 2182 2183 2184 2185 2186
#define SRARI_H4(RTYPE, in0, in1, in2, in3, shift)    \
{                                                     \
    SRARI_H2(RTYPE, in0, in1, shift);                 \
    SRARI_H2(RTYPE, in2, in3, shift);                 \
}
#define SRARI_H4_UH(...) SRARI_H4(v8u16, __VA_ARGS__)
#define SRARI_H4_SH(...) SRARI_H4(v8i16, __VA_ARGS__)

2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211
/* Description : Shift right arithmetic rounded (immediate)
   Arguments   : Inputs  - in0, in1, shift
                 Outputs - in0, in1     (in place)
                 Return Type - as per RTYPE
   Details     : Each element of vector 'in0' is shifted right arithmetic by
                 value in 'shift'.
                 The last discarded bit is added to shifted value for rounding
                 and the result is in place written to 'in0'
                 Similar for other pairs
*/
#define SRARI_W2(RTYPE, in0, in1, shift)              \
{                                                     \
    in0 = (RTYPE) __msa_srari_w((v4i32) in0, shift);  \
    in1 = (RTYPE) __msa_srari_w((v4i32) in1, shift);  \
}
#define SRARI_W2_SW(...) SRARI_W2(v4i32, __VA_ARGS__)

#define SRARI_W4(RTYPE, in0, in1, in2, in3, shift)  \
{                                                   \
    SRARI_W2(RTYPE, in0, in1, shift);               \
    SRARI_W2(RTYPE, in2, in3, shift);               \
}
#define SRARI_W4_SH(...) SRARI_W4(v8i16, __VA_ARGS__)
#define SRARI_W4_SW(...) SRARI_W4(v4i32, __VA_ARGS__)

2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229
/* Description : Multiplication of pairs of vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
   Details     : Each element from 'in0' is multiplied with elements from 'in1'
                 and result is written to 'out0'
                 Similar for other pairs
*/
#define MUL2(in0, in1, in2, in3, out0, out1)  \
{                                             \
    out0 = in0 * in1;                         \
    out1 = in2 * in3;                         \
}
#define MUL4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3)  \
{                                                                             \
    MUL2(in0, in1, in2, in3, out0, out1);                                     \
    MUL2(in4, in5, in6, in7, out2, out3);                                     \
}

2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246
/* Description : Addition of 2 pairs of vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
   Details     : Each element from 2 pairs vectors is added and 2 results are
                 produced
*/
#define ADD2(in0, in1, in2, in3, out0, out1)  \
{                                             \
    out0 = in0 + in1;                         \
    out1 = in2 + in3;                         \
}
#define ADD4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3)  \
{                                                                             \
    ADD2(in0, in1, in2, in3, out0, out1);                                     \
    ADD2(in4, in5, in6, in7, out2, out3);                                     \
}

2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257
/* Description : Subtraction of 2 pairs of vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1
   Details     : Each element from 2 pairs vectors is subtracted and 2 results
                 are produced
*/
#define SUB2(in0, in1, in2, in3, out0, out1)  \
{                                             \
    out0 = in0 - in1;                         \
    out1 = in2 - in3;                         \
}
2258 2259 2260 2261 2262 2263 2264
#define SUB4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3)  \
{                                                                             \
    out0 = in0 - in1;                                                         \
    out1 = in2 - in3;                                                         \
    out2 = in4 - in5;                                                         \
    out3 = in6 - in7;                                                         \
}
2265

2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281
/* Description : Sign extend byte elements from right half of the vector
   Arguments   : Input  - in    (byte vector)
                 Output - out   (sign extended halfword vector)
                 Return Type - signed halfword
   Details     : Sign bit of byte elements from input vector 'in' is
                 extracted and interleaved with same vector 'in' to generate
                 8 halfword elements keeping sign intact
*/
#define UNPCK_R_SB_SH(in, out)                       \
{                                                    \
    v16i8 sign_m;                                    \
                                                     \
    sign_m = __msa_clti_s_b((v16i8) in, 0);          \
    out = (v8i16) __msa_ilvr_b(sign_m, (v16i8) in);  \
}

2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297
/* Description : Sign extend halfword elements from right half of the vector
   Arguments   : Inputs  - in    (input halfword vector)
                 Outputs - out   (sign extended word vectors)
                 Return Type - signed word
   Details     : Sign bit of halfword elements from input vector 'in' is
                 extracted and interleaved with same vector 'in0' to generate
                 4 word elements keeping sign intact
*/
#define UNPCK_R_SH_SW(in, out)                       \
{                                                    \
    v8i16 sign_m;                                    \
                                                     \
    sign_m = __msa_clti_s_h((v8i16) in, 0);          \
    out = (v4i32) __msa_ilvr_h(sign_m, (v8i16) in);  \
}

2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316
/* Description : Sign extend byte elements from input vector and return
                 halfword results in pair of vectors
   Arguments   : Inputs  - in           (1 input byte vector)
                 Outputs - out0, out1   (sign extended 2 halfword vectors)
                 Return Type - signed halfword
   Details     : Sign bit of byte elements from input vector 'in' is
                 extracted and interleaved right with same vector 'in0' to
                 generate 8 signed halfword elements in 'out0'
                 Then interleaved left with same vector 'in0' to
                 generate 8 signed halfword elements in 'out1'
*/
#define UNPCK_SB_SH(in, out0, out1)                  \
{                                                    \
    v16i8 tmp_m;                                     \
                                                     \
    tmp_m = __msa_clti_s_b((v16i8) in, 0);           \
    ILVRL_B2_SH(tmp_m, in, out0, out1);              \
}

2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330
/* Description : Zero extend unsigned byte elements to halfword elements
   Arguments   : Inputs  - in           (1 input unsigned byte vector)
                 Outputs - out0, out1   (unsigned 2 halfword vectors)
                 Return Type - signed halfword
   Details     : Zero extended right half of vector is returned in 'out0'
                 Zero extended left half of vector is returned in 'out1'
*/
#define UNPCK_UB_SH(in, out0, out1)                   \
{                                                     \
    v16i8 zero_m = { 0 };                             \
                                                      \
    ILVRL_B2_SH(zero_m, in, out0, out1);              \
}

2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349
/* Description : Sign extend halfword elements from input vector and return
                 result in pair of vectors
   Arguments   : Inputs  - in           (1 input halfword vector)
                 Outputs - out0, out1   (sign extended 2 word vectors)
                 Return Type - signed word
   Details     : Sign bit of halfword elements from input vector 'in' is
                 extracted and interleaved right with same vector 'in0' to
                 generate 4 signed word elements in 'out0'
                 Then interleaved left with same vector 'in0' to
                 generate 4 signed word elements in 'out1'
*/
#define UNPCK_SH_SW(in, out0, out1)                  \
{                                                    \
    v8i16 tmp_m;                                     \
                                                     \
    tmp_m = __msa_clti_s_h((v8i16) in, 0);           \
    ILVRL_H2_SW(tmp_m, in, out0, out1);              \
}

2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361
/* Description : Swap two variables
   Arguments   : Inputs  - in0, in1
                 Outputs - in0, in1 (in-place)
   Details     : Swapping of two input variables using xor
*/
#define SWAP(in0, in1)  \
{                       \
    in0 = in0 ^ in1;    \
    in1 = in0 ^ in1;    \
    in0 = in0 ^ in1;    \
}

2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375
/* Description : Butterfly of 4 input vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1, out2, out3
   Details     : Butterfly operation
*/
#define BUTTERFLY_4(in0, in1, in2, in3, out0, out1, out2, out3)  \
{                                                                \
    out0 = in0 + in3;                                            \
    out1 = in1 + in2;                                            \
                                                                 \
    out2 = in1 - in2;                                            \
    out3 = in0 - in3;                                            \
}

2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394
/* Description : Butterfly of 8 input vectors
   Arguments   : Inputs  - in0 ...  in7
                 Outputs - out0 .. out7
   Details     : Butterfly operation
*/
#define BUTTERFLY_8(in0, in1, in2, in3, in4, in5, in6, in7,          \
                    out0, out1, out2, out3, out4, out5, out6, out7)  \
{                                                                    \
    out0 = in0 + in7;                                                \
    out1 = in1 + in6;                                                \
    out2 = in2 + in5;                                                \
    out3 = in3 + in4;                                                \
                                                                     \
    out4 = in3 - in4;                                                \
    out5 = in2 - in5;                                                \
    out6 = in1 - in6;                                                \
    out7 = in0 - in7;                                                \
}

2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423
/* Description : Butterfly of 16 input vectors
   Arguments   : Inputs  - in0 ...  in15
                 Outputs - out0 .. out15
   Details     : Butterfly operation
*/
#define BUTTERFLY_16(in0, in1, in2, in3, in4, in5, in6, in7,                \
                     in8, in9,  in10, in11, in12, in13, in14, in15,         \
                     out0, out1, out2, out3, out4, out5, out6, out7,        \
                     out8, out9, out10, out11, out12, out13, out14, out15)  \
{                                                                           \
    out0 = in0 + in15;                                                      \
    out1 = in1 + in14;                                                      \
    out2 = in2 + in13;                                                      \
    out3 = in3 + in12;                                                      \
    out4 = in4 + in11;                                                      \
    out5 = in5 + in10;                                                      \
    out6 = in6 + in9;                                                       \
    out7 = in7 + in8;                                                       \
                                                                            \
    out8 = in7 - in8;                                                       \
    out9 = in6 - in9;                                                       \
    out10 = in5 - in10;                                                     \
    out11 = in4 - in11;                                                     \
    out12 = in3 - in12;                                                     \
    out13 = in2 - in13;                                                     \
    out14 = in1 - in14;                                                     \
    out15 = in0 - in15;                                                     \
}

2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446
/* Description : Transposes input 4x4 byte block
   Arguments   : Inputs  - in0, in1, in2, in3      (input 4x4 byte block)
                 Outputs - out0, out1, out2, out3  (output 4x4 byte block)
                 Return Type - unsigned byte
   Details     :
*/
#define TRANSPOSE4x4_UB_UB(in0, in1, in2, in3, out0, out1, out2, out3)  \
{                                                                       \
    v16i8 zero_m = { 0 };                                               \
    v16i8 s0_m, s1_m, s2_m, s3_m;                                       \
                                                                        \
    ILVR_D2_SB(in1, in0, in3, in2, s0_m, s1_m);                         \
    ILVRL_B2_SB(s1_m, s0_m, s2_m, s3_m);                                \
                                                                        \
    out0 = (v16u8) __msa_ilvr_b(s3_m, s2_m);                            \
    out1 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out0, 4);               \
    out2 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out1, 4);               \
    out3 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out2, 4);               \
}

/* Description : Transposes input 8x4 byte block into 4x8
   Arguments   : Inputs  - in0, in1, in2, in3      (input 8x4 byte block)
                 Outputs - out0, out1, out2, out3  (output 4x8 byte block)
2447
                 Return Type - as per RTYPE
2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466
   Details     :
*/
#define TRANSPOSE8x4_UB(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                        out0, out1, out2, out3)                         \
{                                                                       \
    v16i8 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                               \
                                                                        \
    ILVEV_W2_SB(in0, in4, in1, in5, tmp0_m, tmp1_m);                    \
    tmp2_m = __msa_ilvr_b(tmp1_m, tmp0_m);                              \
    ILVEV_W2_SB(in2, in6, in3, in7, tmp0_m, tmp1_m);                    \
                                                                        \
    tmp3_m = __msa_ilvr_b(tmp1_m, tmp0_m);                              \
    ILVRL_H2_SB(tmp3_m, tmp2_m, tmp0_m, tmp1_m);                        \
                                                                        \
    ILVRL_W2(RTYPE, tmp1_m, tmp0_m, out0, out2);                        \
    out1 = (RTYPE) __msa_ilvl_d((v2i64) out2, (v2i64) out0);            \
    out3 = (RTYPE) __msa_ilvl_d((v2i64) out0, (v2i64) out2);            \
}
#define TRANSPOSE8x4_UB_UB(...) TRANSPOSE8x4_UB(v16u8, __VA_ARGS__)
2467
#define TRANSPOSE8x4_UB_UH(...) TRANSPOSE8x4_UB(v8u16, __VA_ARGS__)
2468

2469 2470 2471 2472 2473
/* Description : Transposes input 8x8 byte block
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7
                           (input 8x8 byte block)
                 Outputs - out0, out1, out2, out3, out4, out5, out6, out7
                           (output 8x8 byte block)
2474
                 Return Type - as per RTYPE
2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493
   Details     :
*/
#define TRANSPOSE8x8_UB(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,   \
                        out0, out1, out2, out3, out4, out5, out6, out7)  \
{                                                                        \
    v16i8 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                                \
    v16i8 tmp4_m, tmp5_m, tmp6_m, tmp7_m;                                \
                                                                         \
    ILVR_B4_SB(in2, in0, in3, in1, in6, in4, in7, in5,                   \
               tmp0_m, tmp1_m, tmp2_m, tmp3_m);                          \
    ILVRL_B2_SB(tmp1_m, tmp0_m, tmp4_m, tmp5_m);                         \
    ILVRL_B2_SB(tmp3_m, tmp2_m, tmp6_m, tmp7_m);                         \
    ILVRL_W2(RTYPE, tmp6_m, tmp4_m, out0, out2);                         \
    ILVRL_W2(RTYPE, tmp7_m, tmp5_m, out4, out6);                         \
    SLDI_B2_0(RTYPE, out0, out2, out1, out3, 8);                         \
    SLDI_B2_0(RTYPE, out4, out6, out5, out7, 8);                         \
}
#define TRANSPOSE8x8_UB_UB(...) TRANSPOSE8x8_UB(v16u8, __VA_ARGS__)
#define TRANSPOSE8x8_UB_UH(...) TRANSPOSE8x8_UB(v8u16, __VA_ARGS__)
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/* Description : Transposes 16x4 block into 4x16 with byte elements in vectors
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7,
                           in8, in9, in10, in11, in12, in13, in14, in15
                 Outputs - out0, out1, out2, out3
                 Return Type - unsigned byte
   Details     :
*/
#define TRANSPOSE16x4_UB_UB(in0, in1, in2, in3, in4, in5, in6, in7,        \
                            in8, in9, in10, in11, in12, in13, in14, in15,  \
                            out0, out1, out2, out3)                        \
{                                                                          \
    v2i64 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                                  \
                                                                           \
    ILVEV_W2_SD(in0, in4, in8, in12, tmp0_m, tmp1_m);                      \
    out1 = (v16u8) __msa_ilvev_d(tmp1_m, tmp0_m);                          \
                                                                           \
    ILVEV_W2_SD(in1, in5, in9, in13, tmp0_m, tmp1_m);                      \
    out3 = (v16u8) __msa_ilvev_d(tmp1_m, tmp0_m);                          \
                                                                           \
    ILVEV_W2_SD(in2, in6, in10, in14, tmp0_m, tmp1_m);                     \
                                                                           \
    tmp2_m = __msa_ilvev_d(tmp1_m, tmp0_m);                                \
    ILVEV_W2_SD(in3, in7, in11, in15, tmp0_m, tmp1_m);                     \
                                                                           \
    tmp3_m = __msa_ilvev_d(tmp1_m, tmp0_m);                                \
    ILVEV_B2_SD(out1, out3, tmp2_m, tmp3_m, tmp0_m, tmp1_m);               \
    out0 = (v16u8) __msa_ilvev_h((v8i16) tmp1_m, (v8i16) tmp0_m);          \
    out2 = (v16u8) __msa_ilvod_h((v8i16) tmp1_m, (v8i16) tmp0_m);          \
                                                                           \
    tmp0_m = (v2i64) __msa_ilvod_b((v16i8) out3, (v16i8) out1);            \
    tmp1_m = (v2i64) __msa_ilvod_b((v16i8) tmp3_m, (v16i8) tmp2_m);        \
    out1 = (v16u8) __msa_ilvev_h((v8i16) tmp1_m, (v8i16) tmp0_m);          \
    out3 = (v16u8) __msa_ilvod_h((v8i16) tmp1_m, (v8i16) tmp0_m);          \
}

2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578
/* Description : Transposes 16x8 block into 8x16 with byte elements in vectors
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7,
                           in8, in9, in10, in11, in12, in13, in14, in15
                 Outputs - out0, out1, out2, out3, out4, out5, out6, out7
                 Return Type - unsigned byte
   Details     :
*/
#define TRANSPOSE16x8_UB_UB(in0, in1, in2, in3, in4, in5, in6, in7,          \
                            in8, in9, in10, in11, in12, in13, in14, in15,    \
                            out0, out1, out2, out3, out4, out5, out6, out7)  \
{                                                                            \
    v16u8 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                                    \
    v16u8 tmp4_m, tmp5_m, tmp6_m, tmp7_m;                                    \
                                                                             \
    ILVEV_D2_UB(in0, in8, in1, in9, out7, out6);                             \
    ILVEV_D2_UB(in2, in10, in3, in11, out5, out4);                           \
    ILVEV_D2_UB(in4, in12, in5, in13, out3, out2);                           \
    ILVEV_D2_UB(in6, in14, in7, in15, out1, out0);                           \
                                                                             \
    tmp0_m = (v16u8) __msa_ilvev_b((v16i8) out6, (v16i8) out7);              \
    tmp4_m = (v16u8) __msa_ilvod_b((v16i8) out6, (v16i8) out7);              \
    tmp1_m = (v16u8) __msa_ilvev_b((v16i8) out4, (v16i8) out5);              \
    tmp5_m = (v16u8) __msa_ilvod_b((v16i8) out4, (v16i8) out5);              \
    out5 = (v16u8) __msa_ilvev_b((v16i8) out2, (v16i8) out3);                \
    tmp6_m = (v16u8) __msa_ilvod_b((v16i8) out2, (v16i8) out3);              \
    out7 = (v16u8) __msa_ilvev_b((v16i8) out0, (v16i8) out1);                \
    tmp7_m = (v16u8) __msa_ilvod_b((v16i8) out0, (v16i8) out1);              \
                                                                             \
    ILVEV_H2_UB(tmp0_m, tmp1_m, out5, out7, tmp2_m, tmp3_m);                 \
    out0 = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m);            \
    out4 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m);            \
                                                                             \
    tmp2_m = (v16u8) __msa_ilvod_h((v8i16) tmp1_m, (v8i16) tmp0_m);          \
    tmp3_m = (v16u8) __msa_ilvod_h((v8i16) out7, (v8i16) out5);              \
    out2 = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m);            \
    out6 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m);            \
                                                                             \
    ILVEV_H2_UB(tmp4_m, tmp5_m, tmp6_m, tmp7_m, tmp2_m, tmp3_m);             \
    out1 = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m);            \
    out5 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m);            \
                                                                             \
    tmp2_m = (v16u8) __msa_ilvod_h((v8i16) tmp5_m, (v8i16) tmp4_m);          \
    tmp2_m = (v16u8) __msa_ilvod_h((v8i16) tmp5_m, (v8i16) tmp4_m);          \
    tmp3_m = (v16u8) __msa_ilvod_h((v8i16) tmp7_m, (v8i16) tmp6_m);          \
    tmp3_m = (v16u8) __msa_ilvod_h((v8i16) tmp7_m, (v8i16) tmp6_m);          \
    out3 = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m);            \
    out7 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m);            \
}

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/* Description : Transposes 4x4 block with half word elements in vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1, out2, out3
                 Return Type - signed halfword
   Details     :
*/
#define TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, out0, out1, out2, out3)  \
{                                                                       \
    v8i16 s0_m, s1_m;                                                   \
                                                                        \
    ILVR_H2_SH(in1, in0, in3, in2, s0_m, s1_m);                         \
    ILVRL_W2_SH(s1_m, s0_m, out0, out2);                                \
    out1 = (v8i16) __msa_ilvl_d((v2i64) out0, (v2i64) out0);            \
    out3 = (v8i16) __msa_ilvl_d((v2i64) out0, (v2i64) out2);            \
}

2595 2596 2597
/* Description : Transposes 8x8 block with half word elements in vectors
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7
                 Outputs - out0, out1, out2, out3, out4, out5, out6, out7
2598
                 Return Type - as per RTYPE
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   Details     :
*/
#define TRANSPOSE8x8_H(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,   \
                       out0, out1, out2, out3, out4, out5, out6, out7)  \
{                                                                       \
    v8i16 s0_m, s1_m;                                                   \
    v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                               \
    v8i16 tmp4_m, tmp5_m, tmp6_m, tmp7_m;                               \
                                                                        \
    ILVR_H2_SH(in6, in4, in7, in5, s0_m, s1_m);                         \
    ILVRL_H2_SH(s1_m, s0_m, tmp0_m, tmp1_m);                            \
    ILVL_H2_SH(in6, in4, in7, in5, s0_m, s1_m);                         \
    ILVRL_H2_SH(s1_m, s0_m, tmp2_m, tmp3_m);                            \
    ILVR_H2_SH(in2, in0, in3, in1, s0_m, s1_m);                         \
    ILVRL_H2_SH(s1_m, s0_m, tmp4_m, tmp5_m);                            \
    ILVL_H2_SH(in2, in0, in3, in1, s0_m, s1_m);                         \
    ILVRL_H2_SH(s1_m, s0_m, tmp6_m, tmp7_m);                            \
    PCKEV_D4(RTYPE, tmp0_m, tmp4_m, tmp1_m, tmp5_m, tmp2_m, tmp6_m,     \
             tmp3_m, tmp7_m, out0, out2, out4, out6);                   \
    out1 = (RTYPE) __msa_pckod_d((v2i64) tmp0_m, (v2i64) tmp4_m);       \
    out3 = (RTYPE) __msa_pckod_d((v2i64) tmp1_m, (v2i64) tmp5_m);       \
    out5 = (RTYPE) __msa_pckod_d((v2i64) tmp2_m, (v2i64) tmp6_m);       \
    out7 = (RTYPE) __msa_pckod_d((v2i64) tmp3_m, (v2i64) tmp7_m);       \
}
#define TRANSPOSE8x8_UH_UH(...) TRANSPOSE8x8_H(v8u16, __VA_ARGS__)
#define TRANSPOSE8x8_SH_SH(...) TRANSPOSE8x8_H(v8i16, __VA_ARGS__)

/* Description : Transposes 4x4 block with word elements in vectors
   Arguments   : Inputs  - in0, in1, in2, in3
                 Outputs - out0, out1, out2, out3
                 Return Type - signed word
   Details     :
*/
#define TRANSPOSE4x4_SW_SW(in0, in1, in2, in3, out0, out1, out2, out3)  \
{                                                                       \
    v4i32 s0_m, s1_m, s2_m, s3_m;                                       \
                                                                        \
    ILVRL_W2_SW(in1, in0, s0_m, s1_m);                                  \
    ILVRL_W2_SW(in3, in2, s2_m, s3_m);                                  \
                                                                        \
    out0 = (v4i32) __msa_ilvr_d((v2i64) s2_m, (v2i64) s0_m);            \
    out1 = (v4i32) __msa_ilvl_d((v2i64) s2_m, (v2i64) s0_m);            \
    out2 = (v4i32) __msa_ilvr_d((v2i64) s3_m, (v2i64) s1_m);            \
    out3 = (v4i32) __msa_ilvl_d((v2i64) s3_m, (v2i64) s1_m);            \
}

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/* Description : Average byte elements from pair of vectors and store 8x4 byte
                 block in destination memory
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride
   Details     : Each byte element from input vector pair 'in0' and 'in1' are
                 averaged (a + b)/2 and stored in 'tmp0_m'
                 Each byte element from input vector pair 'in2' and 'in3' are
                 averaged (a + b)/2 and stored in 'tmp1_m'
                 Each byte element from input vector pair 'in4' and 'in5' are
                 averaged (a + b)/2 and stored in 'tmp2_m'
                 Each byte element from input vector pair 'in6' and 'in7' are
                 averaged (a + b)/2 and stored in 'tmp3_m'
                 The half vector results from all 4 vectors are stored in
                 destination memory as 8x4 byte block
*/
#define AVE_ST8x4_UB(in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride)  \
{                                                                           \
    uint64_t out0_m, out1_m, out2_m, out3_m;                                \
    v16u8 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                                   \
                                                                            \
    tmp0_m = __msa_ave_u_b((v16u8) in0, (v16u8) in1);                       \
    tmp1_m = __msa_ave_u_b((v16u8) in2, (v16u8) in3);                       \
    tmp2_m = __msa_ave_u_b((v16u8) in4, (v16u8) in5);                       \
    tmp3_m = __msa_ave_u_b((v16u8) in6, (v16u8) in7);                       \
                                                                            \
    out0_m = __msa_copy_u_d((v2i64) tmp0_m, 0);                             \
    out1_m = __msa_copy_u_d((v2i64) tmp1_m, 0);                             \
    out2_m = __msa_copy_u_d((v2i64) tmp2_m, 0);                             \
    out3_m = __msa_copy_u_d((v2i64) tmp3_m, 0);                             \
    SD4(out0_m, out1_m, out2_m, out3_m, pdst, stride);                      \
}

/* Description : Average byte elements from pair of vectors and store 16x4 byte
                 block in destination memory
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride
   Details     : Each byte element from input vector pair 'in0' and 'in1' are
                 averaged (a + b)/2 and stored in 'tmp0_m'
                 Each byte element from input vector pair 'in2' and 'in3' are
                 averaged (a + b)/2 and stored in 'tmp1_m'
                 Each byte element from input vector pair 'in4' and 'in5' are
                 averaged (a + b)/2 and stored in 'tmp2_m'
                 Each byte element from input vector pair 'in6' and 'in7' are
                 averaged (a + b)/2 and stored in 'tmp3_m'
                 The results from all 4 vectors are stored in destination
                 memory as 16x4 byte block
*/
#define AVE_ST16x4_UB(in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride)  \
{                                                                            \
    v16u8 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                                    \
                                                                             \
    tmp0_m = __msa_ave_u_b((v16u8) in0, (v16u8) in1);                        \
    tmp1_m = __msa_ave_u_b((v16u8) in2, (v16u8) in3);                        \
    tmp2_m = __msa_ave_u_b((v16u8) in4, (v16u8) in5);                        \
    tmp3_m = __msa_ave_u_b((v16u8) in6, (v16u8) in7);                        \
                                                                             \
    ST_UB4(tmp0_m, tmp1_m, tmp2_m, tmp3_m, pdst, stride);                    \
}

2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730
/* Description : Average rounded byte elements from pair of vectors and store
                 8x4 byte block in destination memory
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride
   Details     : Each byte element from input vector pair 'in0' and 'in1' are
                 average rounded (a + b + 1)/2 and stored in 'tmp0_m'
                 Each byte element from input vector pair 'in2' and 'in3' are
                 average rounded (a + b + 1)/2 and stored in 'tmp1_m'
                 Each byte element from input vector pair 'in4' and 'in5' are
                 average rounded (a + b + 1)/2 and stored in 'tmp2_m'
                 Each byte element from input vector pair 'in6' and 'in7' are
                 average rounded (a + b + 1)/2 and stored in 'tmp3_m'
                 The half vector results from all 4 vectors are stored in
                 destination memory as 8x4 byte block
*/
#define AVER_ST8x4_UB(in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride)  \
{                                                                            \
    uint64_t out0_m, out1_m, out2_m, out3_m;                                 \
    v16u8 tp0_m, tp1_m, tp2_m, tp3_m;                                        \
                                                                             \
    AVER_UB4_UB(in0, in1, in2, in3, in4, in5, in6, in7,                      \
                tp0_m, tp1_m, tp2_m, tp3_m);                                 \
                                                                             \
    out0_m = __msa_copy_u_d((v2i64) tp0_m, 0);                               \
    out1_m = __msa_copy_u_d((v2i64) tp1_m, 0);                               \
    out2_m = __msa_copy_u_d((v2i64) tp2_m, 0);                               \
    out3_m = __msa_copy_u_d((v2i64) tp3_m, 0);                               \
    SD4(out0_m, out1_m, out2_m, out3_m, pdst, stride);                       \
}

2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809
/* Description : Average rounded byte elements from pair of vectors and store
                 16x4 byte block in destination memory
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride
   Details     : Each byte element from input vector pair 'in0' and 'in1' are
                 average rounded (a + b + 1)/2 and stored in 'tmp0_m'
                 Each byte element from input vector pair 'in2' and 'in3' are
                 average rounded (a + b + 1)/2 and stored in 'tmp1_m'
                 Each byte element from input vector pair 'in4' and 'in5' are
                 average rounded (a + b + 1)/2 and stored in 'tmp2_m'
                 Each byte element from input vector pair 'in6' and 'in7' are
                 average rounded (a + b + 1)/2 and stored in 'tmp3_m'
                 The vector results from all 4 vectors are stored in
                 destination memory as 16x4 byte block
*/
#define AVER_ST16x4_UB(in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride)  \
{                                                                             \
    v16u8 t0_m, t1_m, t2_m, t3_m;                                             \
                                                                              \
    AVER_UB4_UB(in0, in1, in2, in3, in4, in5, in6, in7,                       \
                t0_m, t1_m, t2_m, t3_m);                                      \
    ST_UB4(t0_m, t1_m, t2_m, t3_m, pdst, stride);                             \
}

/* Description : Average rounded byte elements from pair of vectors,
                 average rounded with destination and store 8x4 byte block
                 in destination memory
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride
   Details     : Each byte element from input vector pair 'in0' and 'in1' are
                 average rounded (a + b + 1)/2 and stored in 'tmp0_m'
                 Each byte element from input vector pair 'in2' and 'in3' are
                 average rounded (a + b + 1)/2 and stored in 'tmp1_m'
                 Each byte element from input vector pair 'in4' and 'in5' are
                 average rounded (a + b + 1)/2 and stored in 'tmp2_m'
                 Each byte element from input vector pair 'in6' and 'in7' are
                 average rounded (a + b + 1)/2 and stored in 'tmp3_m'
                 The half vector results from all 4 vectors are stored in
                 destination memory as 8x4 byte block
*/
#define AVER_DST_ST8x4_UB(in0, in1, in2, in3, in4, in5, in6, in7,  \
                          pdst, stride)                            \
{                                                                  \
    v16u8 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                          \
    v16u8 dst0_m, dst1_m, dst2_m, dst3_m;                          \
                                                                   \
    LD_UB4(pdst, stride, dst0_m, dst1_m, dst2_m, dst3_m);          \
    AVER_UB4_UB(in0, in1, in2, in3, in4, in5, in6, in7,            \
                tmp0_m, tmp1_m, tmp2_m, tmp3_m);                   \
    AVER_ST8x4_UB(dst0_m, tmp0_m, dst1_m, tmp1_m,                  \
                  dst2_m, tmp2_m, dst3_m, tmp3_m, pdst, stride);   \
}

/* Description : Average rounded byte elements from pair of vectors,
                 average rounded with destination and store 16x4 byte block
                 in destination memory
   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride
   Details     : Each byte element from input vector pair 'in0' and 'in1' are
                 average rounded (a + b + 1)/2 and stored in 'tmp0_m'
                 Each byte element from input vector pair 'in2' and 'in3' are
                 average rounded (a + b + 1)/2 and stored in 'tmp1_m'
                 Each byte element from input vector pair 'in4' and 'in5' are
                 average rounded (a + b + 1)/2 and stored in 'tmp2_m'
                 Each byte element from input vector pair 'in6' and 'in7' are
                 average rounded (a + b + 1)/2 and stored in 'tmp3_m'
                 The vector results from all 4 vectors are stored in
                 destination memory as 16x4 byte block
*/
#define AVER_DST_ST16x4_UB(in0, in1, in2, in3, in4, in5, in6, in7,  \
                           pdst, stride)                            \
{                                                                   \
    v16u8 tmp0_m, tmp1_m, tmp2_m, tmp3_m;                           \
    v16u8 dst0_m, dst1_m, dst2_m, dst3_m;                           \
                                                                    \
    LD_UB4(pdst, stride, dst0_m, dst1_m, dst2_m, dst3_m);           \
    AVER_UB4_UB(in0, in1, in2, in3, in4, in5, in6, in7,             \
                tmp0_m, tmp1_m, tmp2_m, tmp3_m);                    \
    AVER_ST16x4_UB(dst0_m, tmp0_m, dst1_m, tmp1_m,                  \
                   dst2_m, tmp2_m, dst3_m, tmp3_m, pdst, stride);   \
}

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/* Description : Add block 4x4
   Arguments   : Inputs  - in0, in1, in2, in3, pdst, stride
   Details     : Least significant 4 bytes from each input vector are added to
                 the destination bytes, clipped between 0-255 and then stored.
*/
#define ADDBLK_ST4x4_UB(in0, in1, in2, in3, pdst, stride)         \
{                                                                 \
    uint32_t src0_m, src1_m, src2_m, src3_m;                      \
    uint32_t out0_m, out1_m, out2_m, out3_m;                      \
    v8i16 inp0_m, inp1_m, res0_m, res1_m;                         \
    v16i8 dst0_m = { 0 };                                         \
    v16i8 dst1_m = { 0 };                                         \
    v16i8 zero_m = { 0 };                                         \
                                                                  \
    ILVR_D2_SH(in1, in0, in3, in2, inp0_m, inp1_m)                \
    LW4(pdst, stride,  src0_m, src1_m, src2_m, src3_m);           \
    INSERT_W2_SB(src0_m, src1_m, dst0_m);                         \
    INSERT_W2_SB(src2_m, src3_m, dst1_m);                         \
    ILVR_B2_SH(zero_m, dst0_m, zero_m, dst1_m, res0_m, res1_m);   \
    ADD2(res0_m, inp0_m, res1_m, inp1_m, res0_m, res1_m);         \
    CLIP_SH2_0_255(res0_m, res1_m);                               \
    PCKEV_B2_SB(res0_m, res0_m, res1_m, res1_m, dst0_m, dst1_m);  \
                                                                  \
    out0_m = __msa_copy_u_w((v4i32) dst0_m, 0);                   \
    out1_m = __msa_copy_u_w((v4i32) dst0_m, 1);                   \
    out2_m = __msa_copy_u_w((v4i32) dst1_m, 0);                   \
    out3_m = __msa_copy_u_w((v4i32) dst1_m, 1);                   \
    SW4(out0_m, out1_m, out2_m, out3_m, pdst, stride);            \
}

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/* Description : Dot product and addition of 3 signed halfword input vectors
   Arguments   : Inputs  - in0, in1, in2, coeff0, coeff1, coeff2
                 Outputs - out0_m
                 Return Type - signed halfword
   Details     : Dot product of 'in0' with 'coeff0'
                 Dot product of 'in1' with 'coeff1'
                 Dot product of 'in2' with 'coeff2'
                 Addition of all the 3 vector results

                 out0_m = (in0 * coeff0) + (in1 * coeff1) + (in2 * coeff2)
*/
#define DPADD_SH3_SH(in0, in1, in2, coeff0, coeff1, coeff2)         \
( {                                                                 \
    v8i16 tmp1_m;                                                   \
    v8i16 out0_m;                                                   \
                                                                    \
    out0_m = __msa_dotp_s_h((v16i8) in0, (v16i8) coeff0);           \
    out0_m = __msa_dpadd_s_h(out0_m, (v16i8) in1, (v16i8) coeff1);  \
    tmp1_m = __msa_dotp_s_h((v16i8) in2, (v16i8) coeff2);           \
    out0_m = __msa_adds_s_h(out0_m, tmp1_m);                        \
                                                                    \
    out0_m;                                                         \
} )

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/* Description : Pack even elements of input vectors & xor with 128
   Arguments   : Inputs  - in0, in1
                 Outputs - out_m
                 Return Type - unsigned byte
   Details     : Signed byte even elements from 'in0' and 'in1' are packed
                 together in one vector and the resulted vector is xor'ed with
                 128 to shift the range from signed to unsigned byte
*/
#define PCKEV_XORI128_UB(in0, in1)                            \
( {                                                           \
    v16u8 out_m;                                              \
    out_m = (v16u8) __msa_pckev_b((v16i8) in1, (v16i8) in0);  \
    out_m = (v16u8) __msa_xori_b((v16u8) out_m, 128);         \
    out_m;                                                    \
} )

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/* Description : Converts inputs to unsigned bytes, interleave, average & store
                 as 8x4 unsigned byte block
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   Arguments   : Inputs  - in0, in1, in2, in3, dst0, dst1, pdst, stride
2883
*/
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#define CONVERT_UB_AVG_ST8x4_UB(in0, in1, in2, in3,           \
                                dst0, dst1, pdst, stride)     \
{                                                             \
    v16u8 tmp0_m, tmp1_m;                                     \
    uint8_t *pdst_m = (uint8_t *) (pdst);                     \
                                                              \
    tmp0_m = PCKEV_XORI128_UB(in0, in1);                      \
    tmp1_m = PCKEV_XORI128_UB(in2, in3);                      \
    AVER_UB2_UB(tmp0_m, dst0, tmp1_m, dst1, tmp0_m, tmp1_m);  \
    ST8x4_UB(tmp0_m, tmp1_m, pdst_m, stride);                 \
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}

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/* Description : Pack even byte elements, extract 0 & 2 index words from pair
                 of results and store 4 words in destination memory as per
                 stride
   Arguments   : Inputs  - in0, in1, in2, in3, pdst, stride
*/
#define PCKEV_ST4x4_UB(in0, in1, in2, in3, pdst, stride)  \
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{                                                         \
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    uint32_t out0_m, out1_m, out2_m, out3_m;              \
    v16i8 tmp0_m, tmp1_m;                                 \
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                                                          \
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    PCKEV_B2_SB(in1, in0, in3, in2, tmp0_m, tmp1_m);      \
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                                                          \
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    out0_m = __msa_copy_u_w((v4i32) tmp0_m, 0);           \
    out1_m = __msa_copy_u_w((v4i32) tmp0_m, 2);           \
    out2_m = __msa_copy_u_w((v4i32) tmp1_m, 0);           \
    out3_m = __msa_copy_u_w((v4i32) tmp1_m, 2);           \
                                                          \
    SW4(out0_m, out1_m, out2_m, out3_m, pdst, stride);    \
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}
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/* Description : Pack even byte elements and store byte vector in destination
                 memory
   Arguments   : Inputs  - in0, in1, pdst
*/
#define PCKEV_ST_SB(in0, in1, pdst)                   \
{                                                     \
    v16i8 tmp_m;                                      \
    tmp_m = __msa_pckev_b((v16i8) in1, (v16i8) in0);  \
    ST_SB(tmp_m, (pdst));                             \
}
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/* Description : Horizontal 2 tap filter kernel code
   Arguments   : Inputs  - in0, in1, mask, coeff, shift
*/
#define HORIZ_2TAP_FILT_UH(in0, in1, mask, coeff, shift)            \
( {                                                                 \
    v16i8 tmp0_m;                                                   \
    v8u16 tmp1_m;                                                   \
                                                                    \
    tmp0_m = __msa_vshf_b((v16i8) mask, (v16i8) in1, (v16i8) in0);  \
    tmp1_m = __msa_dotp_u_h((v16u8) tmp0_m, (v16u8) coeff);         \
    tmp1_m = (v8u16) __msa_srari_h((v8i16) tmp1_m, shift);          \
    tmp1_m = __msa_sat_u_h(tmp1_m, shift);                          \
                                                                    \
    tmp1_m;                                                         \
} )
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#endif  /* AVUTIL_MIPS_GENERIC_MACROS_MSA_H */