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ffmpeg.wasm-core
Commit 97f074f1 authored by Shivraj Patil's avatar Shivraj Patil Committed by Michael Niedermayer
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avcodec/mips: MSA (MIPS-SIMD-Arch) optimizations for HEVC copy and hv mc functions 

Incorporated review comment.
Removed "__" from volatile.
Signed-off-by: 's avatarShivraj Patil <shivraj.patil@imgtec.com>
Reviewed-by: 's avatarNedeljko Babic <Nedeljko.Babic@imgtec.com>
Signed-off-by: 's avatarMichael Niedermayer <michaelni@gmx.at>
parent 5d914a4a
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libavcodec/mips/hevcdsp_init_mips.c
View file @ 97f074f1
......@@ -25,6 +25,16 @@ static av_cold void hevc_dsp_init_msa(HEVCDSPContext *c,
const int bit_depth)
{
if (8 == bit_depth) {
c->put_hevc_qpel[1][0][0] = ff_hevc_put_hevc_pel_pixels4_8_msa;
c->put_hevc_qpel[2][0][0] = ff_hevc_put_hevc_pel_pixels6_8_msa;
c->put_hevc_qpel[3][0][0] = ff_hevc_put_hevc_pel_pixels8_8_msa;
c->put_hevc_qpel[4][0][0] = ff_hevc_put_hevc_pel_pixels12_8_msa;
c->put_hevc_qpel[5][0][0] = ff_hevc_put_hevc_pel_pixels16_8_msa;
c->put_hevc_qpel[6][0][0] = ff_hevc_put_hevc_pel_pixels24_8_msa;
c->put_hevc_qpel[7][0][0] = ff_hevc_put_hevc_pel_pixels32_8_msa;
c->put_hevc_qpel[8][0][0] = ff_hevc_put_hevc_pel_pixels48_8_msa;
c->put_hevc_qpel[9][0][0] = ff_hevc_put_hevc_pel_pixels64_8_msa;
c->put_hevc_qpel[1][0][1] = ff_hevc_put_hevc_qpel_h4_8_msa;
c->put_hevc_qpel[3][0][1] = ff_hevc_put_hevc_qpel_h8_8_msa;
c->put_hevc_qpel[4][0][1] = ff_hevc_put_hevc_qpel_h12_8_msa;
......@@ -42,6 +52,15 @@ static av_cold void hevc_dsp_init_msa(HEVCDSPContext *c,
c->put_hevc_qpel[7][1][0] = ff_hevc_put_hevc_qpel_v32_8_msa;
c->put_hevc_qpel[8][1][0] = ff_hevc_put_hevc_qpel_v48_8_msa;
c->put_hevc_qpel[9][1][0] = ff_hevc_put_hevc_qpel_v64_8_msa;
c->put_hevc_qpel[1][1][1] = ff_hevc_put_hevc_qpel_hv4_8_msa;
c->put_hevc_qpel[3][1][1] = ff_hevc_put_hevc_qpel_hv8_8_msa;
c->put_hevc_qpel[4][1][1] = ff_hevc_put_hevc_qpel_hv12_8_msa;
c->put_hevc_qpel[5][1][1] = ff_hevc_put_hevc_qpel_hv16_8_msa;
c->put_hevc_qpel[6][1][1] = ff_hevc_put_hevc_qpel_hv24_8_msa;
c->put_hevc_qpel[7][1][1] = ff_hevc_put_hevc_qpel_hv32_8_msa;
c->put_hevc_qpel[8][1][1] = ff_hevc_put_hevc_qpel_hv48_8_msa;
c->put_hevc_qpel[9][1][1] = ff_hevc_put_hevc_qpel_hv64_8_msa;
}
}
#endif // #if HAVE_MSA
......
libavcodec/mips/hevcdsp_mips.h
View file @ 97f074f1
......@@ -29,6 +29,16 @@ void ff_hevc_put_hevc_##PEL##_##DIR####WIDTH##_8_msa(int16_t *dst, \
intptr_t my, \
int width)
MC(pel, pixels, 4);
MC(pel, pixels, 6);
MC(pel, pixels, 8);
MC(pel, pixels, 12);
MC(pel, pixels, 16);
MC(pel, pixels, 24);
MC(pel, pixels, 32);
MC(pel, pixels, 48);
MC(pel, pixels, 64);
MC(qpel, h, 4);
MC(qpel, h, 8);
MC(qpel, h, 12);
......@@ -46,4 +56,14 @@ MC(qpel, v, 24);
MC(qpel, v, 32);
MC(qpel, v, 48);
MC(qpel, v, 64);
MC(qpel, hv, 4);
MC(qpel, hv, 8);
MC(qpel, hv, 12);
MC(qpel, hv, 16);
MC(qpel, hv, 24);
MC(qpel, hv, 32);
MC(qpel, hv, 48);
MC(qpel, hv, 64);
#undef MC
libavcodec/mips/hevcdsp_msa.c
View file @ 97f074f1
This diff is collapsed.
libavutil/mips/generic_macros_msa.h
View file @ 97f074f1
......@@ -50,7 +50,25 @@
*((v8i16 *) (pdest)) = (vec); \
}
#define STORE_SW(vec, pdest) \
{ \
*((v4i32 *) (pdest)) = (vec); \
}
#if (__mips_isa_rev >= 6)
#define STORE_WORD(pdst, val) \
{ \
uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
uint32_t val_m = (val); \
\
__asm__ volatile ( \
"sw %[val_m], %[dst_ptr_m] \n\t" \
\
: [dst_ptr_m] "=m" (*dst_ptr_m) \
: [val_m] "r" (val_m) \
); \
}
#define STORE_DWORD(pdst, val) \
{ \
uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
......@@ -64,6 +82,19 @@
); \
}
#else
#define STORE_WORD(pdst, val) \
{ \
uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
uint32_t val_m = (val); \
\
__asm__ volatile ( \
"usw %[val_m], %[dst_ptr_m] \n\t" \
\
: [dst_ptr_m] "=m" (*dst_ptr_m) \
: [val_m] "r" (val_m) \
); \
}
#define STORE_DWORD(pdst, val) \
{ \
uint8_t *dst1_m = (uint8_t *) (pdst); \
......@@ -83,6 +114,13 @@
}
#endif
#define LOAD_2VECS_SB(psrc, stride, \
val0, val1) \
{ \
val0 = LOAD_SB(psrc + 0 * stride); \
val1 = LOAD_SB(psrc + 1 * stride); \
}
#define LOAD_4VECS_SB(psrc, stride, \
val0, val1, val2, val3) \
{ \
......@@ -92,6 +130,15 @@
val3 = LOAD_SB(psrc + 3 * stride); \
}
#define LOAD_6VECS_SB(psrc, stride, \
out0, out1, out2, out3, out4, out5) \
{ \
LOAD_4VECS_SB((psrc), (stride), \
(out0), (out1), (out2), (out3)); \
LOAD_2VECS_SB((psrc + 4 * stride), (stride), \
(out4), (out5)); \
}
#define LOAD_7VECS_SB(psrc, stride, \
val0, val1, val2, val3, \
val4, val5, val6) \
......@@ -115,6 +162,48 @@
(out4), (out5), (out6), (out7)); \
}
#define STORE_2VECS_SH(ptr, stride, \
in0, in1) \
{ \
STORE_SH(in0, ((ptr) + 0 * stride)); \
STORE_SH(in1, ((ptr) + 1 * stride)); \
}
#define STORE_4VECS_SH(ptr, stride, \
in0, in1, in2, in3) \
{ \
STORE_SH(in0, ((ptr) + 0 * stride)); \
STORE_SH(in1, ((ptr) + 1 * stride)); \
STORE_SH(in2, ((ptr) + 2 * stride)); \
STORE_SH(in3, ((ptr) + 3 * stride)); \
}
#define STORE_6VECS_SH(ptr, stride, \
in0, in1, in2, in3, \
in4, in5) \
{ \
STORE_SH(in0, ((ptr) + 0 * stride)); \
STORE_SH(in1, ((ptr) + 1 * stride)); \
STORE_SH(in2, ((ptr) + 2 * stride)); \
STORE_SH(in3, ((ptr) + 3 * stride)); \
STORE_SH(in4, ((ptr) + 4 * stride)); \
STORE_SH(in5, ((ptr) + 5 * stride)); \
}
#define STORE_8VECS_SH(ptr, stride, \
in0, in1, in2, in3, \
in4, in5, in6, in7) \
{ \
STORE_SH(in0, ((ptr) + 0 * stride)); \
STORE_SH(in1, ((ptr) + 1 * stride)); \
STORE_SH(in2, ((ptr) + 2 * stride)); \
STORE_SH(in3, ((ptr) + 3 * stride)); \
STORE_SH(in4, ((ptr) + 4 * stride)); \
STORE_SH(in5, ((ptr) + 5 * stride)); \
STORE_SH(in6, ((ptr) + 6 * stride)); \
STORE_SH(in7, ((ptr) + 7 * stride)); \
}
#define ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
out0, out1) \
{ \
......@@ -164,6 +253,28 @@
out6, out7); \
}
#define ILVR_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
out0, out1) \
{ \
out0 = __msa_ilvr_h((v8i16) (in0_l), (v8i16) (in0_r)); \
out1 = __msa_ilvr_h((v8i16) (in1_l), (v8i16) (in1_r)); \
}
#define ILVR_H_6VECS_SH(in0_r, in1_r, in2_r, \
in3_r, in4_r, in5_r, \
in0_l, in1_l, in2_l, \
in3_l, in4_l, in5_l, \
out0, out1, out2, \
out3, out4, out5) \
{ \
ILVR_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
out0, out1); \
ILVR_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
out2, out3); \
ILVR_H_2VECS_SH(in4_r, in5_r, in4_l, in5_l, \
out4, out5); \
}
#define ILVL_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
out0, out1) \
{ \
......@@ -196,6 +307,28 @@
out4, out5); \
}
#define ILVL_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
out0, out1) \
{ \
out0 = __msa_ilvl_h((v8i16) (in0_l), (v8i16) (in0_r)); \
out1 = __msa_ilvl_h((v8i16) (in1_l), (v8i16) (in1_r)); \
}
#define ILVL_H_6VECS_SH(in0_r, in1_r, in2_r, \
in3_r, in4_r, in5_r, \
in0_l, in1_l, in2_l, \
in3_l, in4_l, in5_l, \
out0, out1, out2, \
out3, out4, out5) \
{ \
ILVL_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
out0, out1); \
ILVL_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
out2, out3); \
ILVL_H_2VECS_SH(in4_r, in5_r, in4_l, in5_l, \
out4, out5); \
}
#define ILVR_D_2VECS_SB(out0, in0_l, in0_r, \
out1, in1_l, in1_r) \
{ \
......
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