-
Clemens Hammacher authored
With just five cache registers, Liftoff can run out of memory on a 64bit shift. This CL solves this by using a parallel register move and pinning less registers. R=ahaas@chromium.org Bug: chromium:894307 Change-Id: I91ed0fee00ceb452841e5d1bb10905be6702dcce Reviewed-on: https://chromium-review.googlesource.com/c/1337580 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#57552}
59a8eba8
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
arm | ||
arm64 | ||
ia32 | ||
mips | ||
mips64 | ||
ppc | ||
s390 | ||
x64 | ||
DEPS | ||
liftoff-assembler-defs.h | ||
liftoff-assembler.cc | ||
liftoff-assembler.h | ||
liftoff-compiler.cc | ||
liftoff-compiler.h | ||
liftoff-register.h |