-
Ambroise Vincent authored
This includes the instruction opcode, its use in TF, its support in the simulator and the detection of the associated CPU feature. The instruction can be tested in the simulator with the new --sim-arm64-optional-features flag. Change-Id: I6047fa16696394fe0ced4535f7788d2c8716a18c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2222348Reviewed-by: Ross McIlroy <rmcilroy@chromium.org> Reviewed-by: Georg Neis <neis@chromium.org> Commit-Queue: Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#68261}
dfa0f31a
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
disasm-arm64.cc | ||
disasm-arm64.h | ||
eh-frame-arm64.cc |