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Shu-yu Guo authored
To free up some ArchOpcode bits (especially for arm64), encode all atomic opcodes that are duplicated between 32bit and 64bit widths with a single opcode and encode the width in another field. Bug: v8:12093 Change-Id: Ide05e8f0b2aa877ea776851e47df60dd410deae2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3093257Reviewed-by: Zhi An Ng <zhin@chromium.org> Commit-Queue: Shu-yu Guo <syg@chromium.org> Cr-Commit-Position: refs/heads/master@{#76289}
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code-generator-riscv64.cc | ||
instruction-codes-riscv64.h | ||
instruction-scheduler-riscv64.cc | ||
instruction-selector-riscv64.cc |