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Derek Tu authored
Adds the following CB type RISC-V instructions to the assembler: c.beqz, c.bnez, c.andi, c.srai, c.srli. Also removes sext_xlen from RVC instructions c.xor, c.or, c.and. Change-Id: I96ce4693019c28235ccd4f85d0a68ca89a3f4096 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2912922Reviewed-by: Brice Dobry <brice.dobry@futurewei.com> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#74801}
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disasm-riscv64.cc | ||
unwinder-riscv64.cc |