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Zhao Jiazhong authored
Port c0eee179 https://crrev.com/c/2157648 Original Commit Message: ROL will be optional operator as arm, arm64 only have ROR. The reason for this CL is inefficient Wasm codegen for 64-bit left-rotation. Change-Id: I014575d300a97c6fb7dc54d89328fd997d314d92 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2182219Reviewed-by: Tobias Tebbi <tebbi@chromium.org> Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn> Cr-Commit-Position: refs/heads/master@{#67588}
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code-generator-mips64.cc | ||
instruction-codes-mips64.h | ||
instruction-scheduler-mips64.cc | ||
instruction-selector-mips64.cc |