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  1. 16 Mar, 2016 3 commits
  3. 10 Feb, 2016 1 commit
  5. 02 Feb, 2016 1 commit
  7. 28 Jan, 2016 1 commit
  9. 27 Nov, 2015 1 commit
  11. 02 Oct, 2015 3 commits
    • danno's avatar
      Re-reland: Remove register index/code indirection · 5cf1c0bc
      danno authored 
      Previous to this patch, both the lithium and TurboFan register
allocators tracked allocated registers by "indices", rather than
the register codes used elsewhere in the runtime. This patch
ensures that codes are used everywhere, and in the process cleans
up a bunch of redundant code and adds more structure to how the
set of allocatable registers is defined.

Some highlights of changes:

* TurboFan's RegisterConfiguration class moved to V8's top level
  so that it can be shared with Crankshaft.
* Various "ToAllocationIndex" and related methods removed.
* Code that can be easily shared between Register classes on
  different platforms is now shared.
* The list of allocatable registers on each platform is declared
  as a list rather than implicitly via the register index <->
  code mapping.

Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2
Cr-Commit-Position: refs/heads/master@{#30913}

Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf
Cr-Commit-Position: refs/heads/master@{#31075}

Review URL: https://codereview.chromium.org/1287383003

Cr-Commit-Position: refs/heads/master@{#31087}
      5cf1c0bc
    • danno's avatar
      Revert of Reland: Remove register index/code indirection (patchset #20... · 00e07b00
      danno authored 
      Revert of Reland: Remove register index/code indirection (patchset #20 id:380001 of https://codereview.chromium.org/1287383003/ )

Reason for revert:
Failures on MIPS

Original issue's description:
> Remove register index/code indirection
>
> Previous to this patch, both the lithium and TurboFan register
> allocators tracked allocated registers by "indices", rather than
> the register codes used elsewhere in the runtime. This patch
> ensures that codes are used everywhere, and in the process cleans
> up a bunch of redundant code and adds more structure to how the
> set of allocatable registers is defined.
>
> Some highlights of changes:
>
> * TurboFan's RegisterConfiguration class moved to V8's top level
>   so that it can be shared with Crankshaft.
> * Various "ToAllocationIndex" and related methods removed.
> * Code that can be easily shared between Register classes on
>   different platforms is now shared.
> * The list of allocatable registers on each platform is declared
>   as a list rather than implicitly via the register index <->
>   code mapping.
>
> Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2
> Cr-Commit-Position: refs/heads/master@{#30913}
>
> Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf
> Cr-Commit-Position: refs/heads/master@{#31075}

TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true

Review URL: https://codereview.chromium.org/1380863004

Cr-Commit-Position: refs/heads/master@{#31083}
      00e07b00
    • danno's avatar
      Remove register index/code indirection · 7b7a8205
      danno authored 
      Previous to this patch, both the lithium and TurboFan register
allocators tracked allocated registers by "indices", rather than
the register codes used elsewhere in the runtime. This patch
ensures that codes are used everywhere, and in the process cleans
up a bunch of redundant code and adds more structure to how the
set of allocatable registers is defined.

Some highlights of changes:

* TurboFan's RegisterConfiguration class moved to V8's top level
  so that it can be shared with Crankshaft.
* Various "ToAllocationIndex" and related methods removed.
* Code that can be easily shared between Register classes on
  different platforms is now shared.
* The list of allocatable registers on each platform is declared
  as a list rather than implicitly via the register index <->
  code mapping.

Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2
Cr-Commit-Position: refs/heads/master@{#30913}

Review URL: https://codereview.chromium.org/1287383003

Cr-Commit-Position: refs/heads/master@{#31075}
      7b7a8205
  13. 30 Sep, 2015 1 commit
  15. 24 Sep, 2015 2 commits
    • danno's avatar
      Revert of Remove register index/code indirection (patchset #17 id:320001 of... · 3ac27431
      danno authored 
      Revert of Remove register index/code indirection (patchset #17 id:320001 of https://codereview.chromium.org/1287383003/ )

Reason for revert:
Failures on greedy RegAlloc, Fuzzer

Original issue's description:
> Remove register index/code indirection
>
> Previous to this patch, both the lithium and TurboFan register
> allocators tracked allocated registers by "indices", rather than
> the register codes used elsewhere in the runtime. This patch
> ensures that codes are used everywhere, and in the process cleans
> up a bunch of redundant code and adds more structure to how the
> set of allocatable registers is defined.
>
> Some highlights of changes:
>
> * TurboFan's RegisterConfiguration class moved to V8's top level
>   so that it can be shared with Crankshaft.
> * Various "ToAllocationIndex" and related methods removed.
> * Code that can be easily shared between Register classes on
>   different platforms is now shared.
> * The list of allocatable registers on each platform is declared
>   as a list rather than implicitly via the register index <->
>   code mapping.
>
> Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2
> Cr-Commit-Position: refs/heads/master@{#30913}

TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true

Review URL: https://codereview.chromium.org/1365073002

Cr-Commit-Position: refs/heads/master@{#30914}
      3ac27431
    • danno's avatar
      Remove register index/code indirection · 80bc6f6e
      danno authored 
      Previous to this patch, both the lithium and TurboFan register
allocators tracked allocated registers by "indices", rather than
the register codes used elsewhere in the runtime. This patch
ensures that codes are used everywhere, and in the process cleans
up a bunch of redundant code and adds more structure to how the
set of allocatable registers is defined.

Some highlights of changes:

* TurboFan's RegisterConfiguration class moved to V8's top level
  so that it can be shared with Crankshaft.
* Various "ToAllocationIndex" and related methods removed.
* Code that can be easily shared between Register classes on
  different platforms is now shared.
* The list of allocatable registers on each platform is declared
  as a list rather than implicitly via the register index <->
  code mapping.

Review URL: https://codereview.chromium.org/1287383003

Cr-Commit-Position: refs/heads/master@{#30913}
      80bc6f6e
  17. 11 Sep, 2015 1 commit
  19. 31 Jul, 2015 1 commit
  21. 20 Jul, 2015 1 commit
    • yangguo's avatar
      Debugger: prepare code for debugging on a per-function basis. · 35c28ce0
      yangguo authored 
      Prior to this patch, we enter a global debug mode whenever a break point
is set. By entering this mode, all code is deoptimized and activated
frames are recompiled and redirected to newly compiled debug code.

After this patch, we only deoptimize/redirect for functions we want to
debug. Trigger for this is Debug::EnsureDebugInfo, and having DebugInfo
object attached to the SFI prevents optimization/inlining.

The result is that we can have optimized code for functions without break
points alongside functions that do have break points, which are not
optimized.

R=mstarzinger@chromium.org, ulan@chromium.org
BUG=v8:4132
LOG=Y

Review URL: https://codereview.chromium.org/1233073005

Cr-Commit-Position: refs/heads/master@{#29758}
      35c28ce0
  23. 15 Jul, 2015 1 commit
  25. 13 Jul, 2015 1 commit
  27. 09 Jun, 2015 1 commit
    • mbrandy's avatar
      Fix issues with Arm's use of embedded constant pools · e3d76269
      mbrandy authored 
      - Introduce Assembler::DataAlign for table alignment in code object
- Fix several misuses of r8 (alias of the pool pointer register, pp)
- Fix calculation of pp in OSR/handler entry invocation
- Enable missing cases in deserializer
- Fix references to ool constant pools in comments.

R=rmcilroy@chromium.org, michael_dawson@ca.ibm.com
BUG=chromium:497180
LOG=N

Review URL: https://codereview.chromium.org/1155673005

Cr-Commit-Position: refs/heads/master@{#28873}
      e3d76269
  29. 04 Jun, 2015 1 commit
    • mbrandy's avatar
      Add support for Embedded Constant Pools for PPC and Arm · eac7f046
      mbrandy authored 
      Embed constant pools within their corresponding Code
objects.

This removes support for out-of-line constant pools in favor
of the new approach -- the main advantage being that it
eliminates the need to allocate and manage separate constant
pool array objects.

Currently supported on PPC and ARM.  Enabled by default on
PPC only.

This yields a 6% improvment in Octane on PPC64.

R=bmeurer@chromium.org, rmcilroy@chromium.org, michael_dawson@ca.ibm.com
BUG=chromium:478811
LOG=Y

Review URL: https://codereview.chromium.org/1162993006

Cr-Commit-Position: refs/heads/master@{#28801}
      eac7f046
  31. 03 Jun, 2015 1 commit
  33. 02 Jun, 2015 1 commit
    • mbrandy's avatar
      Add support for Embedded Constant Pools for PPC and Arm · a9404029
      mbrandy authored 
      Embed constant pools within their corresponding Code
objects.

This removes support for out-of-line constant pools in favor
of the new approach -- the main advantage being that it
eliminates the need to allocate and manage separate constant
pool array objects.

Currently supported on PPC and ARM.  Enabled by default on
PPC only.

This yields a 6% improvment in Octane on PPC64.

R=danno@chromium.org, svenpanne@chromium.org, bmeurer@chromium.org, rmcilroy@chromium.org, dstence@us.ibm.com, michael_dawson@ca.ibm.com
BUG=chromium:478811
LOG=Y

Review URL: https://codereview.chromium.org/1131783003

Cr-Commit-Position: refs/heads/master@{#28770}
      a9404029
  35. 23 Mar, 2015 1 commit
  37. 18 Mar, 2015 1 commit
  39. 05 Mar, 2015 1 commit
  41. 24 Sep, 2014 1 commit
  43. 21 Aug, 2014 1 commit
  45. 06 Aug, 2014 1 commit
  47. 04 Aug, 2014 1 commit
  49. 15 Jul, 2014 1 commit
  51. 03 Jul, 2014 1 commit
    • rmcilroy@chromium.org's avatar
      [Arm]: Enable use of extended out-of-line constant pool for Arm. · 40af47d4
      rmcilroy@chromium.org authored 
       - Adds support to the Arm assembler to use extended constant pools.
 - Update (set_)target_address_at to support extended constant pool load
   updates.
 - Replace Operand::is_single_instruction with Operand::instructions_required
   Due to the fact that different constant pool load types require different
   numbers of instructions.
 - Various cleanups of ConstantPoolBuilder to cleaner integration of the
   extended constant pool building.
 - Update GetRelocatedValue such that offsets to both map_check and bool_load
   are explicitly provided, rather than location of bool_load being inferred
   based on map_check, since the code inbetween is no longer of a predictable
   size.
 - Update MacroAssembler::GetRelocatedValueLocation() to add support for
   getting a value from an extended constant pool entry.
 - Update Debug::SetAfterBreakTarget() to use target_address_from_return_address
   when checking for debug breaks at constant pool load points.
 - Change ConstantPoolIterateBody to iterate over both heap and code pointer in
   the small section before moving onto the extended section, to work around the
   requirement of the serializer that pointers are iterated in-order.
 - Increase old_pointer_space SizeOfFirstPage() to offset the fact that constant
   pools are now in the old pointer space (rather than code).

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/356393003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22209 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      40af47d4
  53. 30 Jun, 2014 1 commit
  55. 23 Jun, 2014 1 commit
  57. 03 Jun, 2014 1 commit
  59. 20 May, 2014 1 commit
  61. 16 May, 2014 1 commit
    • yangguo@chromium.org's avatar
      Decouple CpuFeatures from serializer state. · fe243379
      yangguo@chromium.org authored 
      Traditionally, we cross compile a snapshot iff the serializer is enabled.
This will change in the future.

Changes:
 - CpuFeatures probing is done once per process, depending on whether we
   cross compile.
 - CpuFeatures are consolidated into the platform-independent assembler.h
   as much as possible.
 - FLAG_enable_<feature> will only be checked at probing time (already the
   case for ARM).
 - The serializer state is cached by the MacroAssembler.
 - PlatformFeatureScope is no longer necessary.
 - CPUFeature enum values no longer map to CPUID bit fields.

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/285233010

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21347 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      fe243379
  63. 06 May, 2014 1 commit
  65. 25 Apr, 2014 1 commit
  67. 19 Mar, 2014 2 commits