- 27 Apr, 2016 1 commit
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jacob.bramley authored
This addresses Cortex-A53 errata 819472, 826319, 827319 and 824069. Note that using "civac" rather than "cvau" doesn't appear to affect performance at all. BUG= Review-Url: https://codereview.chromium.org/1921173004 Cr-Commit-Position: refs/heads/master@{#35828}
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- 22 Mar, 2016 1 commit
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echristo authored
The warning notes that we'd want a 'w' register here because the size of the operand is 32-bit, however, the instruction only takes an 'x' register and so force that using the 'x' modifier on the instruction. BUG= Review URL: https://codereview.chromium.org/1817963003 Cr-Commit-Position: refs/heads/master@{#35008}
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- 16 Mar, 2016 1 commit
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jkummerow authored
along with "[arm64] Fix i/d cache line size confusion typo" and "Fix a warning about inline asm source/destination mismatches..." which were building on it. This reverts the following commits: 8d7399f9 474e6a3d c3ff68b6 Reason for revert: We're getting a large number of crash reports from arm64 devices that are obviously related to cache flushing after code patching. Bisection results say that the problems started at revision c3ff68b6. Since I can't find a bug in that CL except for the typo that I've fixed in 474e6a3d (which made some of the crashes go away but not all of them), we have no choice but to revert the changes in order to get stability under control while we investigate. BUG=chromium:594646 LOG=n Review URL: https://codereview.chromium.org/1806853002 Cr-Commit-Position: refs/heads/master@{#34816}
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- 01 Feb, 2016 1 commit
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mbrandy authored
In the interest of generalization, this change: - Consolidates cache line size detection for all interested architectures under base::CPU (currently leveraged by only PPC and ARM64). - Differentiates between instruction vs data cache line sizes. R=rmcilroy@chromium.org, jochen@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com BUG= Review URL: https://codereview.chromium.org/1643363002 Cr-Commit-Position: refs/heads/master@{#33642}
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- 11 Sep, 2015 1 commit
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mlippautz authored
BUG=chromium:524425 LOG=N Review URL: https://codereview.chromium.org/1332283002 Cr-Commit-Position: refs/heads/master@{#30695}
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- 01 Sep, 2015 1 commit
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mstarzinger authored
This CL us a pure refactoring that makes an empty compilation unit including just "isolate.h" or "contexts.h" but not "objects-inl.h" compile without warnings or errors. This is needed to further reduce the header dependency tangle. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1322883002 Cr-Commit-Position: refs/heads/master@{#30500}
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- 17 Aug, 2015 1 commit
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mstarzinger authored
R=yangguo@chromium.org Review URL: https://codereview.chromium.org/1299563003 Cr-Commit-Position: refs/heads/master@{#30187}
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- 01 Jun, 2015 1 commit
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erikcorry authored
When compiling on a laptop I like to concatenate the small test files. This makes a big difference to compile times. These changes make that easier. R=ulan@chromium.org BUG= Review URL: https://codereview.chromium.org/1163803002 Cr-Commit-Position: refs/heads/master@{#28742}
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- 19 Dec, 2014 1 commit
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arajp authored
Denver supports a coherent cache mechanism. There is no need to clean the D cache and invalidate I cache. MTS has to check the translation anytime there is an I cache invalidate and this time can be saved by making FlushICache a NOP. The patch improves Octane by roughly 3-4% on Denver. Review URL: https://codereview.chromium.org/797233002 Cr-Commit-Position: refs/heads/master@{#25898}
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- 04 Aug, 2014 1 commit
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bmeurer@chromium.org authored
This way we don't clash with the ASSERT* macros defined by GoogleTest, and we are one step closer to being able to replace our homegrown base/ with base/ from Chrome. R=jochen@chromium.org, svenpanne@chromium.org Review URL: https://codereview.chromium.org/430503007 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22812 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 30 Jun, 2014 1 commit
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jochen@chromium.org authored
Also split v8-core independent methods from checks.h to base/logging.h and merge v8checks with the rest of checks. The CPU::FlushICache method is moved to CpuFeatures::FlushICache RoundUp and related methods are moved to base/macros.h Remove all layering violations from src/libplatform BUG=none R=jkummerow@chromium.org LOG=n Review URL: https://codereview.chromium.org/358363002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22092 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 20 Jun, 2014 1 commit
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mstarzinger@chromium.org authored
R=rossberg@chromium.org Review URL: https://codereview.chromium.org/333013002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21894 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 03 Jun, 2014 1 commit
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jochen@chromium.org authored
- this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 16 May, 2014 1 commit
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yangguo@chromium.org authored
Traditionally, we cross compile a snapshot iff the serializer is enabled. This will change in the future. Changes: - CpuFeatures probing is done once per process, depending on whether we cross compile. - CpuFeatures are consolidated into the platform-independent assembler.h as much as possible. - FLAG_enable_<feature> will only be checked at probing time (already the case for ARM). - The serializer state is cached by the MacroAssembler. - PlatformFeatureScope is no longer necessary. - CPUFeature enum values no longer map to CPUID bit fields. R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/285233010 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21347 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 13 May, 2014 1 commit
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rodolph.perfetta@arm.com authored
BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/268673020 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21290 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 09 May, 2014 2 commits
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ishell@chromium.org authored
1) runtime/references checks temporarily disabled (56 items left) 2) other errors fixed R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/277913002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21222 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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rmcilroy@chromium.org authored
Even although the Arm64 specification specifies that csp only needs to be aligned to 16 bytes if it is dereferenced, some implementations show poor performance. Also makes the following change: - Enable CPU support for arm64 to enable probing of cpu implementer and cpu part. - Add ALWAYS_ALIGN_CSP CpuFeature for Arm64 and set it based on runtime probing of the cpu imp - Rename PrepareForPush and PrepareForPop to PushPreamble and PopPostamble and move PopPostabl Original Review URL: https://codereview.chromium.org/264773004 R=ulan@chromium.org Review URL: https://codereview.chromium.org/271543004 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21221 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 07 May, 2014 1 commit
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bmeurer@chromium.org authored
Revert "Arm64: Ensure that csp is always aligned to 16 byte values even if jssp is not." and "Arm64: Fix check errors on Arm64 debug after r21177.". This reverts commit r21177 and r21179 for breaking the arm64 build. TBR=rmcilroy@chromium.org Review URL: https://codereview.chromium.org/271623002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21184 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 06 May, 2014 1 commit
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rmcilroy@chromium.org authored
Even although the Arm64 specification specifies that csp only needs to be aligned to 16 bytes if it is dereferenced, some implementations show poor performance if csp is every set to a non-aligned value. This CL ensures that csp is always aligned to 16 byte values on these platforms and adds checks to ensure this in debug mode. Also makes the following change: - Enable CPU support for arm64 to enable probing of cpu implementer and cpu part. - Add ALWAYS_ALIGN_CSP CpuFeature for Arm64 and set it based on runtime probing of the cpu implementer. - Rename PrepareForPush and PrepareForPop to PushPreamble and PopPostamble and move PopPostable after the pop. - R=jacob.bramley@arm.com, ulan@chromium.org Review URL: https://codereview.chromium.org/264773004 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21177 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 02 May, 2014 1 commit
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svenpanne@chromium.org authored
This disentagles the initialization/dependency mess quite a bit and makes things vastly simpler. If the 'mrs' on every flush is too expensive (which it is hopefully not), the cache line sizes will have to be instance variables of the CPU class and FlushICache will have to be a member function. This would involve some more or less tricky refactorings, which we shouldn't do until we are *really* forced to do. BUG=359977 LOG=y R=rodolph.perfetta@gmail.com Review URL: https://codereview.chromium.org/269543016 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21119 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 29 Apr, 2014 1 commit
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bmeurer@chromium.org authored
R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/259183002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21035 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 28 Apr, 2014 1 commit
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svenpanne@chromium.org authored
This is a necessary intermediate step to disentangle the startup. In the long run CPU and CpuFeatures should probably be merged, and Serializer::enabled usage should be radically reduced, but we're not there yet. BUG=359977 LOG=y R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/258993002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21001 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 21 Mar, 2014 1 commit
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jochen@chromium.org authored
BUG=354405 R=ulan@chromium.org, rodolph.perfetta@arm.com LOG=y Review URL: https://codereview.chromium.org/207823003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20148 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 12 Feb, 2014 1 commit
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ulan@chromium.org authored
BUG=v8:3113 LOG=Y R=jochen@chromium.org, rmcilroy@chromium.org, rodolph.perfetta@arm.com Review URL: https://codereview.chromium.org/148293020 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19311 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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