1. 27 Apr, 2016 1 commit
  2. 22 Mar, 2016 1 commit
  3. 16 Mar, 2016 1 commit
    • jkummerow's avatar
      Revert "Detect cache line size on Linux for PPC hosts." · 5d62db74
      jkummerow authored
      along with "[arm64] Fix i/d cache line size confusion typo"
      and "Fix a warning about inline asm source/destination mismatches..."
      which were building on it.
      
      This reverts the following commits:
      8d7399f9
      474e6a3d
      c3ff68b6
      
      Reason for revert: We're getting a large number of crash reports from
      arm64 devices that are obviously related to cache flushing after code
      patching. Bisection results say that the problems started at revision
      c3ff68b6. Since I can't find a bug in that CL except for the typo that
      I've fixed in 474e6a3d (which made some of the crashes go away but not
      all of them), we have no choice but to revert the changes in order to
      get stability under control while we investigate.
      
      BUG=chromium:594646
      LOG=n
      
      Review URL: https://codereview.chromium.org/1806853002
      
      Cr-Commit-Position: refs/heads/master@{#34816}
      5d62db74
  4. 01 Feb, 2016 1 commit
    • mbrandy's avatar
      Detect cache line size on Linux for PPC hosts. · c3ff68b6
      mbrandy authored
      In the interest of generalization, this change:
      - Consolidates cache line size detection for all interested
        architectures under base::CPU (currently leveraged by only
        PPC and ARM64).
      - Differentiates between instruction vs data cache line sizes.
      
      R=rmcilroy@chromium.org, jochen@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
      BUG=
      
      Review URL: https://codereview.chromium.org/1643363002
      
      Cr-Commit-Position: refs/heads/master@{#33642}
      c3ff68b6
  5. 11 Sep, 2015 1 commit
  6. 01 Sep, 2015 1 commit
  7. 17 Aug, 2015 1 commit
  8. 01 Jun, 2015 1 commit
  9. 19 Dec, 2014 1 commit
    • arajp's avatar
      Make FlushICache NOP for Nvidia Denver CPU's. · f4fb7025
      arajp authored
      Denver supports a coherent cache mechanism. There is no need to clean
      the D cache and invalidate I cache. MTS has to check the translation
      anytime there is an I cache invalidate and this time can be saved by
      making FlushICache a NOP.
      
      The patch improves Octane by roughly 3-4% on Denver.
      
      Review URL: https://codereview.chromium.org/797233002
      
      Cr-Commit-Position: refs/heads/master@{#25898}
      f4fb7025
  10. 04 Aug, 2014 1 commit
  11. 30 Jun, 2014 1 commit
  12. 20 Jun, 2014 1 commit
  13. 03 Jun, 2014 1 commit
  14. 16 May, 2014 1 commit
    • yangguo@chromium.org's avatar
      Decouple CpuFeatures from serializer state. · fe243379
      yangguo@chromium.org authored
      Traditionally, we cross compile a snapshot iff the serializer is enabled.
      This will change in the future.
      
      Changes:
       - CpuFeatures probing is done once per process, depending on whether we
         cross compile.
       - CpuFeatures are consolidated into the platform-independent assembler.h
         as much as possible.
       - FLAG_enable_<feature> will only be checked at probing time (already the
         case for ARM).
       - The serializer state is cached by the MacroAssembler.
       - PlatformFeatureScope is no longer necessary.
       - CPUFeature enum values no longer map to CPUID bit fields.
      
      R=svenpanne@chromium.org
      
      Review URL: https://codereview.chromium.org/285233010
      
      git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21347 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      fe243379
  15. 13 May, 2014 1 commit
  16. 09 May, 2014 2 commits
  17. 07 May, 2014 1 commit
  18. 06 May, 2014 1 commit
    • rmcilroy@chromium.org's avatar
      Arm64: Ensure that csp is always aligned to 16 byte values even if jssp is not. · 53bf1268
      rmcilroy@chromium.org authored
      Even although the Arm64 specification specifies that csp
      only needs to be aligned to 16 bytes if it is dereferenced, some implementations show poor performance if csp is every set to a non-aligned value.  This CL ensures that csp is always aligned to 16 byte values on these platforms and adds checks to ensure this in debug mode.
      
      Also makes the following change:
       - Enable CPU support for arm64 to enable probing of cpu implementer and cpu part.
       - Add ALWAYS_ALIGN_CSP CpuFeature for Arm64 and set it based on runtime probing of the cpu implementer.
       - Rename PrepareForPush and PrepareForPop to PushPreamble and PopPostamble and move PopPostable after the pop.
       -
      
      R=jacob.bramley@arm.com, ulan@chromium.org
      
      Review URL: https://codereview.chromium.org/264773004
      
      git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21177 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      53bf1268
  19. 02 May, 2014 1 commit
  20. 29 Apr, 2014 1 commit
  21. 28 Apr, 2014 1 commit
  22. 21 Mar, 2014 1 commit
  23. 12 Feb, 2014 1 commit