- 26 May, 2020 2 commits
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Milad Farazmand authored
Change-Id: I5a93231b16c8291c87fce57062837dce886bc2f8 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2216231Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67975}
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Victor Gomes authored
This CL is a step towards reversing JS stack arguments for TurboFan. It does the following: 1. Add StackOrder to CallInterfaceDescriptor 2. Reverse arguments in TF backend for JS calls. 3. Cleanup TFJ builtins interface descriptors, since calls for these builtins already reverse the arguments, we don't need to reverse the interface descriptor anymore. Change-Id: Ie840b1757bf023aa381a7fa01cbe66e7cf90778f Bug: v8:10201 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2213440Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Victor Gomes <victorgomes@chromium.org> Cr-Commit-Position: refs/heads/master@{#67971}
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- 25 May, 2020 1 commit
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Ross McIlroy authored
We can't consistently rewire the successor blocks of an unreachable node to disconnect them from the graph when we are trying to maintain the schedule. Instead simply leave the code there. As a future optimization we could add a proper scheduled dead code elimination phase which can deal with this. As a side-effect, one of the tests sees a int64 DeadValue, so add support for that in the instruction selector. BUG=chromium:1083272,chromium:1083763,chromium:1084953,v8:9684 Change-Id: I69a6feaeef4eae62110392e27ea848b28bccf787 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2209061 Commit-Queue: Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Auto-Submit: Ross McIlroy <rmcilroy@chromium.org> Cr-Commit-Position: refs/heads/master@{#67953}
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- 22 May, 2020 1 commit
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Seth Brenith authored
Sometimes CSA code carefully constructs a mask to check several bitfields at once. Thus far, such a check has been very awkward to write in Torque. This change adds a way to do so, using the non-short-circuiting binary `&` operator. So now you can write an expression that depends on several bitfields from a bitfield struct, like `x.a == 5 & x.b & !x.c & x.d == 2` (assuming b is a one-bit value), and it will be reduced to a single mask and equality check. To demonstrate a usage of this new reduction, this change ports the trivial macro IsSimpleObjectMap to Torque. I manually verified that the generated code for the builtin SetDataProperties, which uses that macro, is unchanged. Bug: v8:7793 Change-Id: I4a23e0005d738a6699ea0f2a63f9fd67b01e7026 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2183276 Commit-Queue: Seth Brenith <seth.brenith@microsoft.com> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Cr-Commit-Position: refs/heads/master@{#67948}
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- 21 May, 2020 3 commits
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Ng Zhi An authored
From 10 to 8 instructions (each). We do this by using mi (instead of lt) and ls (instead of le), which check for strictly less than and greater than or unordered. That way we don't have to have an extra mov for NaN. Change-Id: I18ff876ac12b7097d73d6cbbb64de6c2a1148e43 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2208934Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67947}
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Ng Zhi An authored
The proposal uses the lane shape, e.g. i64x2.anytrue, and we were using s1x2.anytrue in our opcodes. This was a legacy naming, because we were trying to bitpack the booleans. Now that we aren't doing that, rename these to be more consistent with the proposal. This was done with a straightforward sed script, changing both cpp code and also some comments in mjsunit test files. Bug: v8:10506 Change-Id: If077ed805de23520d8580d6b3b1906c80f67b94f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2207915 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Cr-Commit-Position: refs/heads/master@{#67945}
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Seth Brenith authored
Currently, if d8 is run with the --turbo-profiling flag, it prints info about every TurboFan-compiled function. This info includes the number of times that each basic block in the function was run. It also includes text representations of the function's schedule and code, so that the person reading the output can associate counters with blocks of code. The data about each function is currently stored in a BasicBlockProfiler::Data instance, which is attached to a list owned by the singleton BasicBlockProfiler. Each Data contains an std::vector<uint32_t> which represents how many times each block in the function has executed. The generated code for each block uses a raw pointer into the storage of that vector to implement incrementing the counter. With this change, if you compile with v8_enable_builtins_profiling and then run with --turbo-profiling, d8 will print that same info about builtins too. In order to generate code that can survive being serialized to a snapshot and reloaded, this change uses counters in the JS heap instead of a std::vector outside the JS heap. The steps for instrumentation are as follows: 1. Between scheduling and instruction selection, add code to increment the counter for each block. The counters array doesn't yet exist at this point, and allocation is disallowed, so at this point the code refers to a special marker value. 2. During finalization of the code, allocate a BasicBlockProfilingData object on the JS heap containing data equivalent to what is stored in BasicBlockProfiler::Data. This includes a ByteArray that is big enough to store the counters for each block. 3. Patch the reference in the BuiltinsConstantsTableBuilder so that instead of referring to the marker object, it now refers to this ByteArray. Also add the BasicBlockProfilingData object to a list that is attached to the heap roots so it can be easily accessed for printing. Because these steps include modifying the BuiltinsConstantsTableBuilder, this procedure is only applicable to builtins. Runtime-generated code still uses raw pointers into std::vector instances. In order to keep divergence between these code paths to a minimum, most work is done referring to instances of BasicBlockProfiler::Data (the C++ class), and functions are provided to copy back and forth between that type and BasicBlockProfilingData (the JS heap object). This change is intended only to make --turbo-profiling work consistently on more kinds of functions, but with some further work, this data could form the basis for: - code coverage info for fuzzers, and/or - hot-path info for profile-guided optimization. Bug: v8:10470, v8:9119 Change-Id: Ib556a5bc3abe67cdaa2e3ee62702a2a08b11cb61 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2159738 Commit-Queue: Seth Brenith <seth.brenith@microsoft.com> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#67944}
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- 19 May, 2020 2 commits
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Ng Zhi An authored
Bug: v8:10501 Change-Id: Ib61f7957e1fd7cfa498bce28171b5f9e4b2f93c3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2191393 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#67913}
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Ng Zhi An authored
For load extends, we can use Ldr, which does not require us to manually calculate address - ld1r uses post-index, so we have to add the index ourselves. By checking the operation in the instruction-selector, we can set the addressing mode for load extends to be MRR, then use Ldr in the codegen. Bug: v8:9886 Change-Id: Ibcd22fa719cd6dafd2fd06e68066960db249b57a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2207656Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67912}
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- 18 May, 2020 1 commit
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Ng Zhi An authored
The codegen uses a bunch of vpmax to try and keep set bits around. The datatype for vpmax does not need to change for each instruction, since vpmax U32 will persist set bits just as well. This simplifies the instruction sequences for S1x8 and S1x16 anytrue. I added a test to check a special case when a f64x2 contains -0.0 (top bit set). A previous attempt to optimize codegen used floating point compare, which does not distinguish between 0.0 and -0.0. So -0.0 will compare equals to 0.0, and incorrect return 0 for anytrue. Change-Id: I66013796af08a666009e6b2d774ea7ee7bdfe1ad Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2203113 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#67875}
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- 15 May, 2020 1 commit
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Milad Farazmand authored
Also modified simd ExtractLane to use the input lane. Change-Id: Icc40226c1f3e001eb588e8c44570399c19582404 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2199643Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67826}
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- 14 May, 2020 1 commit
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Ng Zhi An authored
This only changes iterator type specifiers and cast expressions. See https://clang.llvm.org/extra/clang-tidy/checks/modernize-use-auto.html for more on this warning. Bug: v8:10488 Change-Id: I1e6747aafb24fd2d9d946e054fb20fbd1d8e5b26 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2191921Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67814}
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- 13 May, 2020 4 commits
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Ng Zhi An authored
Bug: v8:10501 Change-Id: I6dad0f4da4d7c50d0793d39a5a119defb6b53844 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2191392 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#67787}
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Ng Zhi An authored
The AVX implementation does not have dst == input(0), so the vminps call was wrong. The intention is to compare the 2 input operands. Bug: chromium:1081030 Change-Id: Id54074327a6aca4b75988fc9d85beccfeabfc791 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2194471Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67786}
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Ambroise Vincent authored
Fold distinct MUL and ADD (or SUB) instructions into a single MLA (or MLS) instruction, mirroring what is being done for general purpose registers. SIMD wasm only uses the vectorized ADD and MUL instructions on quad vectors (NEON Q), so only those cases are handled. SIMD wasm only uses MUL by vectors, not by elements so there is no need to check for an addition and shift reduction. Change-Id: If07191dde9fb1dc37a5de27187800c15cc4325ea Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2184239Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Zhi An Ng <zhin@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#67770}
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Yolanda Chen authored
[regalloc] Do not spill uses that are constrained to move to register in backwards spilling heuristics For uses that are moved to registers, they are not beneficial for backwards spilling as it will introduce memory loads from stack to register. Bug: chromium:1066869, chromium:1063831 Change-Id: I562d22336b6607a8f7286fc65dbf5b95a941a130 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2172052Reviewed-by:
Sigurd Schneider <sigurds@chromium.org> Reviewed-by:
Thibaud Michaud <thibaudm@chromium.org> Commit-Queue: Yolanda Chen <yolanda.chen@intel.com> Cr-Commit-Position: refs/heads/master@{#67765}
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- 11 May, 2020 3 commits
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Ng Zhi An authored
Same implementation as the one for x64 in https://crrev.com/c/2186630. Bug: v8:10501 Change-Id: If2b6c0fdc649afba3449d9579452cf7047a55a54 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2188556Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67721}
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Santiago Aboy Solanes authored
It will now return true for 32-bit constants as well. When enabling this, two errors popped up: one in dissassembler where we might have null hosts, and one in remembered set where we should be compressing the address before storing. As a drive-by: make ppc use full objects until their pointer compression implementation is fully done. Bug: v8:7703 Change-Id: I70f05f952d4e1305fe1fe030755f01f74ea5e5dc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2187622Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Commit-Queue: Santiago Aboy Solanes <solanes@chromium.org> Cr-Commit-Position: refs/heads/master@{#67711}
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Clemens Backes authored
Also, rename the WASM_COMPILED frame type to just WASM. R=jkummerow@chromium.org Bug: v8:10389 Change-Id: I71f16f41a69f8b0295ba34bd7d7fad71729546f2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2187613 Commit-Queue: Clemens Backes <clemensb@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#67698}
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- 08 May, 2020 2 commits
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Ng Zhi An authored
This patch implements f32x4.pmin, f32x4.pmax, f64x2.pmin, and f64x2.pmax for x64 and interpreter. Pseudo-min and Pseudo-max instructions were proposed in https://github.com/WebAssembly/simd/pull/122. These instructions exactly match std::min and std::max in C++ STL, and thus have different semantics from the existing min and max. The instruction-selector for x64 switches the operands around, because it allows for defining the dst to be same as first (really the second input node), allowing better codegen. For example, b = f32x4.pmin(a, b) directly maps to vminps(b, b, a) or minps(b, a), as long as we can define dst == b, and switching the instruction operands around allows us to do that. Bug: v8:10501 Change-Id: I06f983fc1764caf673e600ac91d9c0ac5166e17e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2186630 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#67688}
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Yolanda Chen authored
When pick state from predecessor, we should consider live ranges that were split out by the backwards spilling heurisitics and already end before the predecessor does. Bug: chromium:1066869 Change-Id: I9ff85e73059a7c07f1e212fdc041450c79a4d70c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2174337Reviewed-by:
Thibaud Michaud <thibaudm@chromium.org> Reviewed-by:
Sigurd Schneider <sigurds@chromium.org> Commit-Queue: Yolanda Chen <yolanda.chen@intel.com> Cr-Commit-Position: refs/heads/master@{#67665}
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- 07 May, 2020 2 commits
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Milad Farazmand authored
Change-Id: Ic71dda9c487b6afa95ba2525518c923f2608fd7d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2187003Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67661}
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Mike Stanton authored
We know the array CodeGenerator::deoptimization_literals_ is corrupted somehow. Additional checks in place to validate. Bug: chromium:1027130 Change-Id: Ie0146003f096d24e67aeb382372bca8472548c2a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2182636 Commit-Queue: Michael Stanton <mvstanton@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#67641}
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- 06 May, 2020 4 commits
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Junliang Yan authored
Bug: v8:7703 Change-Id: If2d5c2da1d653247f49e5dfb2e50850b97119b20 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2170798Reviewed-by:
Igor Sheludko <ishell@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Junliang Yan <jyan@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67629}
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Milad Farazmand authored
This CL introduces VOR and VSRO opcodes which get used for implementing F64x2Splat, I64x2Splat and F32x4Splat. Change-Id: I64b4cd340fbe9ecf6a789a91e3219b6ad83ce3f3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2184830Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67627}
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Clemens Backes authored
Interpreter entry compilation was removed in https://crrev.com/c/2172962. This CL removes the {WasmInterpreterEntryFrame} and the corresponding {WASM_INTERPRETER_ENTRY} code kind. Some follow-up cleanups are left as TODOs. R=jkummerow@chromium.org,bmeurer@chromium.org Bug: v8:10389 Change-Id: I1a43eba1ac1a751e05990c688088d99fc901231f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2182456Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#67607}
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Zhao Jiazhong authored
Port c0eee179 https://crrev.com/c/2157648 Original Commit Message: ROL will be optional operator as arm, arm64 only have ROR. The reason for this CL is inefficient Wasm codegen for 64-bit left-rotation. Change-Id: I014575d300a97c6fb7dc54d89328fd997d314d92 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2182219Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn> Cr-Commit-Position: refs/heads/master@{#67588}
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- 05 May, 2020 3 commits
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Ng Zhi An authored
It was assuming that the input is always a register, but it isn't. Bug: chromium:1078399 Change-Id: If14abb8ea34f9febfc04a67a8da260a7e66af7f1 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2182176Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67578}
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Andreas Haas authored
The existing implementation needed uses of the outputs of an AtomicExchange to allocate registers for the result value. However, these uses are not guaranteed to exist. With this CL temp registers get allocated if the uses don't exist. R=gdeepti@chromium.org Bug: chromium:1077130 Change-Id: I058ee53b87c6e995c9f490f3aebbfdba69934f3c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2179503Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#67556}
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Dan Elphick authored
Also makes memory-chunk.h accessible from outside heap which allows removal of some heap-inl.h includes. Bug: v8:10473, v8:10496 Change-Id: Iec4fc5ce8ad201f6ee5fd924cc3cd935324429fc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2172088 Commit-Queue: Jakob Gruber <jgruber@chromium.org> Auto-Submit: Dan Elphick <delphick@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Cr-Commit-Position: refs/heads/master@{#67551}
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- 01 May, 2020 2 commits
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Milad Farazmand authored
Port c0eee179 Original Commit Message: ROL will be optional operator as arm, arm64 only have ROR. The reason for this CL is inefficient Wasm codegen for 64-bit left-rotation. R=duongn@microsoft.com, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com BUG= LOG=N Change-Id: I2803237712e45235ac53be07a28b4dc0c0f4a329 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2173574Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67521}
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Z Nguyen-Huu authored
ROL will be optional operator as arm, arm64 only have ROR. The reason for this CL is inefficient Wasm codegen for 64-bit left-rotation. Bug: v8:10216 Change-Id: I0cd13e4b6de5276a0d0b80eac5ed9c2e52ba1f96 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2157648 Commit-Queue: Z Nguyen-Huu <duongn@microsoft.com> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#67518}
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- 29 Apr, 2020 1 commit
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Tobias Tebbi authored
This is a reland of 43b885a8 This fixes another signed overflow in the unit test. Original change's description: > Reland "[turbofan][csa] optimize Smi untagging better" > > This is a reland of ff22ae80 > > Original change's description: > > [turbofan][csa] optimize Smi untagging better > > > > - Introduce new operator variants for signed right-shifts with the > > additional information that they always shift out zeros. > > - Use these new operators for Smi untagging. > > - Merge left-shifts with a preceding Smi-untagging shift. > > - Optimize comparisons of Smi-untagging shifts to operate on the > > unshifted word. > > - Optimize 64bit comparisons of values expanded from 32bit to use > > a 32bit comparison instead. > > - Change CodeStubAssembler::UntagSmi to first sign-extend and then > > right-shift to enable better address computations for Smi indices. > > > > Bug: v8:9962 > > Change-Id: If91300f365e8f01457aebf0bd43bdf88b305c460 > > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2135734 > > Commit-Queue: Tobias Tebbi <tebbi@chromium.org> > > Reviewed-by: Georg Neis <neis@chromium.org> > > Cr-Commit-Position: refs/heads/master@{#67378} > > Bug: v8:9962 > Change-Id: Ieab0755806c95fb50022eb17596fb0c95f36004c > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2170001 > Commit-Queue: Tobias Tebbi <tebbi@chromium.org> > Commit-Queue: Georg Neis <neis@chromium.org> > Auto-Submit: Tobias Tebbi <tebbi@chromium.org> > Reviewed-by: Georg Neis <neis@chromium.org> > Cr-Commit-Position: refs/heads/master@{#67430} Bug: v8:9962 TBR: neis@chromium.org Change-Id: I79883db546bf37873b3727b8023ef688507091d9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2169103 Commit-Queue: Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#67464}
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- 28 Apr, 2020 3 commits
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Clemens Backes authored
This reverts commit 43b885a8. Reason for revert: Still fails on UBSan: https://ci.chromium.org/p/v8/builders/ci/V8%20Linux64%20UBSan/10873 Original change's description: > Reland "[turbofan][csa] optimize Smi untagging better" > > This is a reland of ff22ae80 > > Original change's description: > > [turbofan][csa] optimize Smi untagging better > > > > - Introduce new operator variants for signed right-shifts with the > > additional information that they always shift out zeros. > > - Use these new operators for Smi untagging. > > - Merge left-shifts with a preceding Smi-untagging shift. > > - Optimize comparisons of Smi-untagging shifts to operate on the > > unshifted word. > > - Optimize 64bit comparisons of values expanded from 32bit to use > > a 32bit comparison instead. > > - Change CodeStubAssembler::UntagSmi to first sign-extend and then > > right-shift to enable better address computations for Smi indices. > > > > Bug: v8:9962 > > Change-Id: If91300f365e8f01457aebf0bd43bdf88b305c460 > > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2135734 > > Commit-Queue: Tobias Tebbi <tebbi@chromium.org> > > Reviewed-by: Georg Neis <neis@chromium.org> > > Cr-Commit-Position: refs/heads/master@{#67378} > > Bug: v8:9962 > Change-Id: Ieab0755806c95fb50022eb17596fb0c95f36004c > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2170001 > Commit-Queue: Tobias Tebbi <tebbi@chromium.org> > Commit-Queue: Georg Neis <neis@chromium.org> > Auto-Submit: Tobias Tebbi <tebbi@chromium.org> > Reviewed-by: Georg Neis <neis@chromium.org> > Cr-Commit-Position: refs/heads/master@{#67430} TBR=neis@chromium.org,tebbi@chromium.org Change-Id: I49e19811ebcecb846f61291bc0c4a0d8b0bc4cff No-Presubmit: true No-Tree-Checks: true No-Try: true Bug: v8:9962 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2168876Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#67431}
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Tobias Tebbi authored
This is a reland of ff22ae80 Original change's description: > [turbofan][csa] optimize Smi untagging better > > - Introduce new operator variants for signed right-shifts with the > additional information that they always shift out zeros. > - Use these new operators for Smi untagging. > - Merge left-shifts with a preceding Smi-untagging shift. > - Optimize comparisons of Smi-untagging shifts to operate on the > unshifted word. > - Optimize 64bit comparisons of values expanded from 32bit to use > a 32bit comparison instead. > - Change CodeStubAssembler::UntagSmi to first sign-extend and then > right-shift to enable better address computations for Smi indices. > > Bug: v8:9962 > Change-Id: If91300f365e8f01457aebf0bd43bdf88b305c460 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2135734 > Commit-Queue: Tobias Tebbi <tebbi@chromium.org> > Reviewed-by: Georg Neis <neis@chromium.org> > Cr-Commit-Position: refs/heads/master@{#67378} Bug: v8:9962 Change-Id: Ieab0755806c95fb50022eb17596fb0c95f36004c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2170001 Commit-Queue: Tobias Tebbi <tebbi@chromium.org> Commit-Queue: Georg Neis <neis@chromium.org> Auto-Submit: Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#67430}
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Zhao Jiazhong authored
Due to lack of testing environment before, there are some bugs in the implementations of wasm-simd on mips64 platform, this CL fix them according to the test on Loongson 3A4000. Change-Id: I59ab6315987fc94a06cf0bf23754f5c593879532 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2162416 Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn> Reviewed-by:
Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#67413}
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- 27 Apr, 2020 1 commit
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Milad Farazmand authored
This CL introduces a new XX1-Form instruction as well as separates VX-Form instructions to be used for implementing simd Splat: - I32x4 - I8x16 - I16x8 Change-Id: If81bbc87b45993ba6fa3e0146dd34496e247dd50 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2165866Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67393}
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- 24 Apr, 2020 3 commits
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Bill Budge authored
This reverts commit ff22ae80. Reason for revert: new test fails on UBSAN https://ci.chromium.org/p/v8/builders/ci/V8%20Linux64%20UBSan/10831 Original change's description: > [turbofan][csa] optimize Smi untagging better > > - Introduce new operator variants for signed right-shifts with the > additional information that they always shift out zeros. > - Use these new operators for Smi untagging. > - Merge left-shifts with a preceding Smi-untagging shift. > - Optimize comparisons of Smi-untagging shifts to operate on the > unshifted word. > - Optimize 64bit comparisons of values expanded from 32bit to use > a 32bit comparison instead. > - Change CodeStubAssembler::UntagSmi to first sign-extend and then > right-shift to enable better address computations for Smi indices. > > Bug: v8:9962 > Change-Id: If91300f365e8f01457aebf0bd43bdf88b305c460 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2135734 > Commit-Queue: Tobias Tebbi <tebbi@chromium.org> > Reviewed-by: Georg Neis <neis@chromium.org> > Cr-Commit-Position: refs/heads/master@{#67378} TBR=neis@chromium.org,tebbi@chromium.org Change-Id: I2617d7a44e5ae33fd79322d37c8b722c00162d22 No-Presubmit: true No-Tree-Checks: true No-Try: true Bug: v8:9962 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2165873Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#67380}
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Tobias Tebbi authored
- Introduce new operator variants for signed right-shifts with the additional information that they always shift out zeros. - Use these new operators for Smi untagging. - Merge left-shifts with a preceding Smi-untagging shift. - Optimize comparisons of Smi-untagging shifts to operate on the unshifted word. - Optimize 64bit comparisons of values expanded from 32bit to use a 32bit comparison instead. - Change CodeStubAssembler::UntagSmi to first sign-extend and then right-shift to enable better address computations for Smi indices. Bug: v8:9962 Change-Id: If91300f365e8f01457aebf0bd43bdf88b305c460 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2135734 Commit-Queue: Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#67378}
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Ng Zhi An authored
We change a bunch of static_cast to a cleaner and shorter brace initialization. I did not change every use of static_cast in the files, just those that relate to SIMD, so as to not cause churn in the diff/blame. Change-Id: I7e90c1b81f09a1e7a3ae7c9825db4fdbd21db919 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2159737Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67373}
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