- 16 Feb, 2016 1 commit
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rodolph.perfetta authored
Let me know if this is not the right approach Review URL: https://codereview.chromium.org/1698483002 Cr-Commit-Position: refs/heads/master@{#34028}
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- 02 Oct, 2015 3 commits
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf Cr-Commit-Position: refs/heads/master@{#31075} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31087}
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danno authored
Revert of Reland: Remove register index/code indirection (patchset #20 id:380001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on MIPS Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} > > Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf > Cr-Commit-Position: refs/heads/master@{#31075} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1380863004 Cr-Commit-Position: refs/heads/master@{#31083}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31075}
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- 30 Sep, 2015 1 commit
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mstarzinger authored
This enables linter checking for "readability/namespace" violations during presubmit and instead marks the few known exceptions that we allow explicitly. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1371083003 Cr-Commit-Position: refs/heads/master@{#31019}
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- 24 Sep, 2015 2 commits
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danno authored
Revert of Remove register index/code indirection (patchset #17 id:320001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on greedy RegAlloc, Fuzzer Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1365073002 Cr-Commit-Position: refs/heads/master@{#30914}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#30913}
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- 11 Aug, 2015 1 commit
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mstarzinger authored
This is the first step of turning the v8.h file into a normal header instead of an include-the-world header. The new rule is that no other header files are allowed to include v8.h, which is enforced by DEPS. Also the number of includes inside the v8.h file has been drastically reduced. Basically the last missing piece is the inclusion of the big objects-inl.h file. This in turn makes many headers follow the IWYU principle. R=bmeurer@chromium.org,hpayer@chromium.org,titzer@chromium.org Review URL: https://codereview.chromium.org/1282503003 Cr-Commit-Position: refs/heads/master@{#30102}
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- 15 May, 2015 1 commit
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martyn.capewell authored
Enable clang's shorten-64-to-32 warning flag on ARM64, and fix the warnings that arise. BUG= Review URL: https://codereview.chromium.org/1131573006 Cr-Commit-Position: refs/heads/master@{#28412}
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- 04 Aug, 2014 1 commit
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bmeurer@chromium.org authored
This way we don't clash with the ASSERT* macros defined by GoogleTest, and we are one step closer to being able to replace our homegrown base/ with base/ from Chrome. R=jochen@chromium.org, svenpanne@chromium.org Review URL: https://codereview.chromium.org/430503007 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22812 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 30 Jul, 2014 1 commit
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danno@chromium.org authored
R=mstarzinger@chromium.org Review URL: https://codereview.chromium.org/426233002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22709 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 02 Jul, 2014 1 commit
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m.m.capewell@googlemail.com authored
Improve the code used to check for encodable logical immediates, fix some corner cases associated with moving kWMinInt into W registers, and add tests. BUG= R=ulan@chromium.org Review URL: https://codereview.chromium.org/364653003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22148 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 01 Jul, 2014 2 commits
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yangguo@chromium.org authored
This reverts r22120 due to build breakage of arm64.debug target. TBR=m.m.capewell@googlemail.com Review URL: https://codereview.chromium.org/361973002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22123 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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m.m.capewell@googlemail.com authored
Improve the code used to check for encodable logical immediates, fix some corner cases associated with moving kWMinInt into W registers, and add tests. BUG= R=ulan@chromium.org Review URL: https://codereview.chromium.org/341123003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22120 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 20 Jun, 2014 1 commit
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mstarzinger@chromium.org authored
R=rossberg@chromium.org Review URL: https://codereview.chromium.org/333013002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21894 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 03 Jun, 2014 1 commit
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jochen@chromium.org authored
- this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 29 Apr, 2014 1 commit
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bmeurer@chromium.org authored
R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/259183002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21035 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 21 Mar, 2014 1 commit
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jochen@chromium.org authored
BUG=354405 R=ulan@chromium.org, rodolph.perfetta@arm.com LOG=y Review URL: https://codereview.chromium.org/207823003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20148 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 18 Mar, 2014 1 commit
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alexandre.rames@arm.com authored
Below are notes about some of the TODOs handled. * In Simulator::Debug: We haven't had issues with printing in the debugger for a while. If the feature turns out to be still lacking an issue can be raised. * In SubStringStub::Generate: There is no need to jump there. The StringCharAtGenerator is asked to set the result in x0, and the return sequence following only uses two instructions. Also, we would need to jump after the native counter increment instead of the return_x0 label. * In ArrayPushStub::Generate: Raised an internal issue to check and update the ARM code. * In MacroAssembler::CopyBytes: The new code should be faster for bulk copies. Raised an internal issue to investigate and improve this function. * In MacroAssembler::EnterExitFrame: Unless we actually find something is wrong, this is working and looks ok. Also fixed the comments about the FP registers. * Comment for BumpSystemStackPointer: Removed the comment at the declaration site and updated the TODO in the implementation. R=ulan@chromium.org Review URL: https://codereview.chromium.org/196473021 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20034 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 14 Mar, 2014 1 commit
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jacob.bramley@arm.com authored
- Return the correct NaN when an invalid operation generates a NaN. - When one or more operands are NaN, handle them as the processor would, prioritising signalling NaNs and making them quiet. - Fix fmadd and related instructions: - Fnmadd is fma(-n, m, -a), not -fma(n, m, a). - Some common libc implementations incorrectly implement fma for zero results, so work around these cases. - Replace some unreliable tests. This patch also adds support for Default-NaN mode, since once all the other work was done, it only required a couple of lines of code. Default-NaN mode was used for an optimisation in ARM, and it should now be possible to apply the same optimisation to A64. BUG= R=jochen@chromium.org Review URL: https://codereview.chromium.org/199083005 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19927 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 12 Feb, 2014 1 commit
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ulan@chromium.org authored
BUG=v8:3113 LOG=Y R=jochen@chromium.org, rmcilroy@chromium.org, rodolph.perfetta@arm.com Review URL: https://codereview.chromium.org/148293020 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19311 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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