- 17 Aug, 2020 1 commit
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Ng Zhi An authored
In Liftoff, we were missing kS128 cases to load to/from stack. For the x64 and ARM64 instruction selector, the calculation of reverse_slot is incorrect for 128-bit values: - reverse_slot += 2 (size of 128-bit values, 2 pointers) - this copies from slot -2 into register - but the value starts at slot -1, it occupies slots -1 and -2 - we end up copying slot -2 (most significant half) of the register, and also slot -3, which is where rsi was store (Wasm instance addr) - the test ends up with a different result every time The calculation of reverse_slot is changed to follow how ia32 and ARM does it, which is to start with - reverse_slot = 0 - in the code-generator, add 1 to the slot - then after emitting Peek operation, reverse_slot += 2 The fixes for x64 and ARM64 are in both instruction-selector and code-generator. ia32 and ARM didn't support writing kSimd128 values yet, it was only a missing check in code-generator, so add that in. For ARM, the codegen is more involved, vld1 does not support addressing with an offset, so we have to do the addition into a scratch register. Also adding a test for returning multiple v128. V128 is not exposed to JavaScript, so we use a Wasm function call, and then an involved chain of extract lanes, returning 6 i32 which we verify the values of. It extracts the first and last lane of the i32x4 value in order to catch bugs where we write or read to a wrong stack slot (off by 1). The simd-scalar-lowering for kCall was only handling single s128 return, we adopt the way i64-lowering handles kCall, so that is can now handle any kinds of calls with s128 in the descriptor. Bug: v8:10794 Bug: chromium:1115230 Change-Id: I2ccdd55f6292bc5794be78053b27e14da8cce70e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2355189 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#69439}
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- 11 Aug, 2020 1 commit
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Seth Brenith authored
I noticed a pattern that has been copied around to various places and thought a helper function might be appropriate. Change-Id: I8944ac5166c649f15c09f587308406cab317b8d4 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2346766Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Seth Brenith <seth.brenith@microsoft.com> Cr-Commit-Position: refs/heads/master@{#69344}
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- 31 Jul, 2020 2 commits
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Ng Zhi An authored
Also add some simple unittests for these functions. Bug: v8:10696 Change-Id: Ic7607780b4eaf275b20d0937bf214846bf51d539 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2330806Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#69183}
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Ng Zhi An authored
Some of these functions will be reused by Liftoff. Move them into simd-shuffle for sharing (even though these only apply to ia32 and x64). Bug: v8:10696 Change-Id: Ib83a2fcd443f93f86d7a4c85898205edb8c3925c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2330796Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#69180}
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- 30 Jul, 2020 1 commit
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Ng Zhi An authored
Change all the callers in backend specific instruction-selector to call the functions in simd-shuffle.h Also copy over the documentation that was in instruction-selector.h to simd-shuffle.h. Bug: v8:10696 Change-Id: Ic9339d6481316f18c19f35c45460e700b45ec38e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2327182 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#69150}
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- 16 Jul, 2020 1 commit
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Ng Zhi An authored
SSE requires operand0 to be a register, since we don't have memory alignment yet. AVX can have performance issues for unaligned access. Bug: v8:9198,chromium:1106285 Change-Id: Ic587d9e0d601664cf6010061d74b22740ba47702 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2303590Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#68906}
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- 14 Jul, 2020 1 commit
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Ng Zhi An authored
There is a sign-extension bug happening when packing 2 32-bit ints into a 64-bit int. We are OR-ing int32_t with a uint64_t, so an integral conversion converts int32_t to uint64_t, which is a sign extension, and this gives unexpected results for a negative value: 0x80000000 | uint64_t{0} -> 0xffffffff80000000 What we want is 0x0000000080000000. Created a helper function to do this work of combining two uint32_t into one uint64_t. The use of this function will also ensure that if callers passed a int32_t, it would first be converted to a uint32_t, and will not have this sign extension bug. Sneaked a small regression test into the existing v128.const cctest, and also cleanup the loop to reset `expected` array to 0. Bug: chromium:1104033 Change-Id: Icaca4c5ba42077dd4463697b9220cdbca9974b5e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2293044 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#68850}
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- 10 Jul, 2020 1 commit
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Igor Sheludko authored
... by migrating old-style code MyObject* obj = new (zone) MyObject(...) to the new style MyObject* obj = zone->New<MyObject>(...) Bug: v8:10689 Change-Id: Iea6c1225ee672035763d8141292a40874658d270 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2288864 Commit-Queue: Igor Sheludko <ishell@chromium.org> Reviewed-by:
Maya Lekova <mslekova@chromium.org> Cr-Commit-Position: refs/heads/master@{#68788}
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- 08 Jul, 2020 1 commit
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Ng Zhi An authored
And removed the ifdef guards around instruction-selector and tests since v128.const is now implemented for x86, x64, arm, arm64. Bug: v8:8460 Change-Id: I0ed8aede0a07db2fd286bf0c3385eba1079558f8 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2285149 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#68745}
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- 07 Jul, 2020 1 commit
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Ng Zhi An authored
Drive-by fix for x64 to remove unused temporary register. Bug: v8:8460 Change-Id: Ib4e83bad4e14670ccd93dd10e16c5483eb0897b8 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2283233 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#68724}
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- 30 Jun, 2020 1 commit
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Jake Hughes authored
Whether or not a store requires a write barrier depends on several invariants within V8. Some flags can break these invariants. In particular, it's not possible to use enable_single_generation with incremental marking because marking barriers are omitted in places where it is assumed an object will be allocated in the young generation. This CL introduces a new flag, enable_unconditional_write_barriers, which allows us to specify that full write barriers should always happens. The main purpose of this is to support single generation GC with incremental marking, but it can also aid as a debugging tool to check for missed write barriers. Bug: v8:10614 Change-Id: I3ab640436bcefc118c9c5c34765421cb9ea4896f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2270546Reviewed-by:
Anton Bikineev <bikineev@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Reviewed-by:
Michael Lippautz <mlippautz@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Commit-Queue: Jake Hughes <jakehughes@google.com> Cr-Commit-Position: refs/heads/master@{#68623}
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- 19 Jun, 2020 1 commit
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Ng Zhi An authored
This implements I32x4DotI16x8S for ia32. Also fixes instruction-selector for SIMD ops, they should all set operand1 to be a register, since we do not have memory alignment yet. Bug: v8:10583 Change-Id: Id273816efd5eea128580f3f7bde533a8e1b2435d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2231031 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#68444}
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- 15 Jun, 2020 1 commit
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Ng Zhi An authored
Implements f32x4 and f64x2 ceil, floor, trunc, nearestint for ia32. Bug: v8:10553 Change-Id: I272c20441297b9aebd39bc7ff96870b40e8ac653 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2227257 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#68347}
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- 03 Jun, 2020 1 commit
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Ng Zhi An authored
Bug: v8:10506 Change-Id: I896d0d614524bb9515593fb1fb2b1e3e9892a026 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2225938Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#68122}
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- 27 May, 2020 1 commit
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Ng Zhi An authored
all_true uses pcmpeqd which takes a memory operand, but needs to be 128-bit aligned, which we don't support yet. Bug: v8:9198 Change-Id: Ia0caaaa76b1103ba538252181ef93e8557fb4739 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2218887Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#68027}
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- 21 May, 2020 1 commit
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Ng Zhi An authored
The proposal uses the lane shape, e.g. i64x2.anytrue, and we were using s1x2.anytrue in our opcodes. This was a legacy naming, because we were trying to bitpack the booleans. Now that we aren't doing that, rename these to be more consistent with the proposal. This was done with a straightforward sed script, changing both cpp code and also some comments in mjsunit test files. Bug: v8:10506 Change-Id: If077ed805de23520d8580d6b3b1906c80f67b94f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2207915 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Cr-Commit-Position: refs/heads/master@{#67945}
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- 13 May, 2020 1 commit
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Ng Zhi An authored
The AVX implementation does not have dst == input(0), so the vminps call was wrong. The intention is to compare the 2 input operands. Bug: chromium:1081030 Change-Id: Id54074327a6aca4b75988fc9d85beccfeabfc791 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2194471Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67786}
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- 11 May, 2020 2 commits
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Ng Zhi An authored
Same implementation as the one for x64 in https://crrev.com/c/2186630. Bug: v8:10501 Change-Id: If2b6c0fdc649afba3449d9579452cf7047a55a54 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2188556Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67721}
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Clemens Backes authored
Also, rename the WASM_COMPILED frame type to just WASM. R=jkummerow@chromium.org Bug: v8:10389 Change-Id: I71f16f41a69f8b0295ba34bd7d7fad71729546f2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2187613 Commit-Queue: Clemens Backes <clemensb@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#67698}
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- 05 May, 2020 2 commits
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Ng Zhi An authored
It was assuming that the input is always a register, but it isn't. Bug: chromium:1078399 Change-Id: If14abb8ea34f9febfc04a67a8da260a7e66af7f1 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2182176Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67578}
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Dan Elphick authored
Also makes memory-chunk.h accessible from outside heap which allows removal of some heap-inl.h includes. Bug: v8:10473, v8:10496 Change-Id: Iec4fc5ce8ad201f6ee5fd924cc3cd935324429fc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2172088 Commit-Queue: Jakob Gruber <jgruber@chromium.org> Auto-Submit: Dan Elphick <delphick@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Cr-Commit-Position: refs/heads/master@{#67551}
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- 01 May, 2020 1 commit
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Z Nguyen-Huu authored
ROL will be optional operator as arm, arm64 only have ROR. The reason for this CL is inefficient Wasm codegen for 64-bit left-rotation. Bug: v8:10216 Change-Id: I0cd13e4b6de5276a0d0b80eac5ed9c2e52ba1f96 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2157648 Commit-Queue: Z Nguyen-Huu <duongn@microsoft.com> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#67518}
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- 24 Apr, 2020 1 commit
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Ng Zhi An authored
We change a bunch of static_cast to a cleaner and shorter brace initialization. I did not change every use of static_cast in the files, just those that relate to SIMD, so as to not cause churn in the diff/blame. Change-Id: I7e90c1b81f09a1e7a3ae7c9825db4fdbd21db919 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2159737Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67373}
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- 06 Apr, 2020 1 commit
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Ng Zhi An authored
This relands commit 7d955faa. Changed the test case to use i16x8 splat instead of i8x16 splat, the latter was causing issues when doing scalar lowering. This change still causes the regression test to fail without the fix. Original change's description: > [wasm-simd][x64][ia32] Do not overwrite input register > > We are ovewriting input register (contains the shift) when we are > masking it, instead, move to a temporary,then mask it. > > Bug: chromium:1065599 > Change-Id: Iab72b94581239447e444746681387350b576e24a > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2125941 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> > Cr-Commit-Position: refs/heads/master@{#66997} Bug: chromium:1065599 Change-Id: I0dc78ddb013652ef88c07d065c3f6877937c5300 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2136220Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67026}
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- 03 Apr, 2020 3 commits
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Zhi An Ng authored
This reverts commit 7d955faa. Reason for revert: Bad change, modified wrong test file https://ci.chromium.org/p/v8/builders/ci/V8%20Linux/36416 Original change's description: > [wasm-simd][x64][ia32] Do not overwrite input register > > We are ovewriting input register (contains the shift) when we are > masking it, instead, move to a temporary,then mask it. > > Bug: chromium:1065599 > Change-Id: Iab72b94581239447e444746681387350b576e24a > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2125941 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> > Cr-Commit-Position: refs/heads/master@{#66997} TBR=gdeepti@chromium.org,zhin@chromium.org Change-Id: I50c57906d6eb49758584b477c971179ea3c6e5d3 No-Presubmit: true No-Tree-Checks: true No-Try: true Bug: chromium:1065599 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2134655Reviewed-by:
Zhi An Ng <zhin@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#67000}
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Ng Zhi An authored
We are ovewriting input register (contains the shift) when we are masking it, instead, move to a temporary,then mask it. Bug: chromium:1065599 Change-Id: Iab72b94581239447e444746681387350b576e24a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2125941 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#66997}
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Ng Zhi An authored
Implement i8x16.bitmask, i16x8.bitmask, i32x4.bitmask on ia32. Drive by additions of disasm and disasm tests to some instructions. Bug: v8:10308 Change-Id: I3725ed6959ae55f96ee7950130776a4f08e177c9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2127314Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#66989}
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- 31 Mar, 2020 1 commit
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Clemens Backes authored
If we want external people to stop shouting WASM, we should start by avoiding that in our own code base. This CL replaces almost all occurrences of "WASM" by "Wasm". The last remaining ones (in frames.cc) are in capitalized contexts where WASM fits. TBR=ecmziegler@chromium.org Bug: v8:10155 Change-Id: I905b92220768b99bb5e1165255691ffe4498dba3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2126917 Commit-Queue: Clemens Backes <clemensb@chromium.org> Reviewed-by:
Emanuel Ziegler <ecmziegler@chromium.org> Cr-Commit-Position: refs/heads/master@{#66917}
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- 30 Mar, 2020 1 commit
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Ng Zhi An authored
Bug: v8:9561 Bug: v8:10115 Change-Id: Iecec52c353e958a95e5508719cd7bd447ecc7bcc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2125507Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#66915}
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- 25 Mar, 2020 1 commit
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Seth Brenith authored
This reverts commit 0c72c719. Reason for revert: Wasm code size increase because not all pipelines use CommonOperatorReducer Original change's description: > Move branch inversion on ==0 into platform-agnostic reducer > > This change is based on a discussion from > https://crrev.com/c/v8/v8/+/2053769/4/src/compiler/machine-operator-reducer.cc#1696 > wherein Tobias suggested moving the folding away of ==0 operations out > of the platform-specific instruction selectors and into the > MachineOperatorReducer. I noticed that CommonOperatorReducer already > handles some very similar cases, so I have tried putting the ==0 folding > into CommonOperatorReducer instead. I'm happy to move it into > MachineOperatorReducer if that's better; I still don't have a very good > understanding of how roles are separated among reducers. > > Change-Id: Ia0285bd9fafeef29d87cc88654bd6d355d467e8f > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2076498 > Commit-Queue: Seth Brenith <seth.brenith@microsoft.com> > Reviewed-by: Tobias Tebbi <tebbi@chromium.org> > Reviewed-by: Clemens Backes <clemensb@chromium.org> > Reviewed-by: Georg Neis <neis@chromium.org> > Cr-Commit-Position: refs/heads/master@{#66688} # Not skipping CQ checks because original CL landed > 1 day ago. Bug: chromium:1061767 Change-Id: Id1fdfb38357eb514d92ed3be0a683f077202faa4 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2117789 Commit-Queue: Seth Brenith <seth.brenith@microsoft.com> Reviewed-by:
Georg Neis <neis@chromium.org> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Cr-Commit-Position: refs/heads/master@{#66862}
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- 17 Mar, 2020 2 commits
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Ng Zhi An authored
This optimizes i8x16 shifts when shift value is constant. It reduces instruction counts from 10 to 6 (unsigned), and 9 to 5 (signed). We can use a word (16-bit) shift, then mask away the high (shru) or low (shl) bits to achieve a byte shift. Most of the instructions are dedicated to building the mask. Bug: v8:10115 Change-Id: Ie602c2b0a7227181502fadb14e100bb0b92f322f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2103445 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#66755}
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Ng Zhi An authored
Delegate to macro assembler functions to pick between SSE or AVX. This simplifies the optimization of constant shifts later. Bug: v8:10115 Change-Id: If0b7dc83a68f2d7839c65527a3b6a62310ace6dd Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2103443Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#66753}
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- 12 Mar, 2020 1 commit
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Seth Brenith authored
This change is based on a discussion from https://crrev.com/c/v8/v8/+/2053769/4/src/compiler/machine-operator-reducer.cc#1696 wherein Tobias suggested moving the folding away of ==0 operations out of the platform-specific instruction selectors and into the MachineOperatorReducer. I noticed that CommonOperatorReducer already handles some very similar cases, so I have tried putting the ==0 folding into CommonOperatorReducer instead. I'm happy to move it into MachineOperatorReducer if that's better; I still don't have a very good understanding of how roles are separated among reducers. Change-Id: Ia0285bd9fafeef29d87cc88654bd6d355d467e8f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2076498 Commit-Queue: Seth Brenith <seth.brenith@microsoft.com> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#66688}
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- 28 Feb, 2020 2 commits
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Ambroise Vincent authored
The ArchLookupSwitch implementation has been completely replaced by ArchBinarySearchSwitch, leaving dead code behind. Change-Id: I7fd6306cb0f5562c10e32293f5ea13bbd3bf7067 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2077684 Commit-Queue: Rodolph Perfetta <rodolph.perfetta@arm.com> Reviewed-by:
Michael Stanton <mvstanton@chromium.org> Cr-Commit-Position: refs/heads/master@{#66501}
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Ng Zhi An authored
Implements i8x16.abs, i16x8.abs, and i32x4.abs. Bug: v8:10233 Change-Id: I573c9969ed0ccc9dfe7ff6bde4fcddb5ffdaa789 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2067844Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#66492}
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- 10 Feb, 2020 1 commit
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Pierre Langlois authored
Each assembler has it's own way to place breakpoints: - stop() for arm, mips*, ppc* and s390. - debug() for arm64. - int3() for ia32 and x64. We can mandate a macro-assembler `DebugBreak()` method that all should implement so one can place a breakpoint in a portable way using a macro-assembler. This way also assemblers are in line with TurboFan, CSA, Torque and Liftoff which all have a DebugBreak() facility. Change-Id: Ic4332bd19ca4db53e01441d54af6632c2c1189f1 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2020954Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#66198}
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- 07 Feb, 2020 1 commit
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Ng Zhi An authored
Bug: v8:10115 Change-Id: If2ef0cd4bef9805dce3c9486d91385d0d40189fb Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2044650Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#66181}
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- 06 Feb, 2020 1 commit
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Ng Zhi An authored
Define a macro in code-generator-ia32 to help identify cases when the shift value is an immediate/constant. In those cases we can directly emit the shifts without any masking, since the instruction selector would have modulo-ed the shift value. We also don't need any temporaries in this case. Bug: v8:10115 Change-Id: I3cdef493fd7c365c733a85ad31b86e2d258b6429 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2037649Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#66162}
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- 04 Feb, 2020 2 commits
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Andreas Haas authored
The instruction selector assumed for Word32AtomicPairCompareExchange nodes that if there exists a Projection(1) user, then there also exists a Projection(0) user. This, however, is not the case, because TurboFan eliminates unreachable nodes. The missing projection node lead to a failed DCHECK in the register allocator. With this CL we allocate the right registers for the existing projections, and allocate the other needed registers as temp registers. R=gdeepti@chromium.org Bug: v8:10140 Change-Id: Id50768c3cb712db5e0eb3b9dcd0a8a479e20953a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2030731Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#66122}
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Ng Zhi An authored
The implementation is pretty much the same, and we instead delegate to a macro assembler to decide if we want the sse or avx instruction. This unification will simplify optimization of constant shifts later on. Bug: v8:10115 Change-Id: I68e60cb3fd51156438989812be189f71e6e47ba7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2026470Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#66121}
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