- 22 Oct, 2015 1 commit
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chunyang.dai authored
register configurations currently. This CL provides a mechanism so that optimizing compilers can select different Register Configuration. BUG= Review URL: https://codereview.chromium.org/1405673003 Cr-Commit-Position: refs/heads/master@{#31476}
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- 08 Oct, 2015 1 commit
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jacob.bramley authored
This fixes several warnings when cross-building using GCC (since r31087, 5cf1c0bc). In particular, CPURegister::code() now returns 'int', matching the other platforms (and the coding style guide). The rest of the patch consists of similar changes to make this work. BUG= Review URL: https://codereview.chromium.org/1393043003 Cr-Commit-Position: refs/heads/master@{#31176}
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- 02 Oct, 2015 3 commits
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf Cr-Commit-Position: refs/heads/master@{#31075} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31087}
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danno authored
Revert of Reland: Remove register index/code indirection (patchset #20 id:380001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on MIPS Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} > > Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf > Cr-Commit-Position: refs/heads/master@{#31075} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1380863004 Cr-Commit-Position: refs/heads/master@{#31083}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31075}
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- 24 Sep, 2015 2 commits
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danno authored
Revert of Remove register index/code indirection (patchset #17 id:320001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on greedy RegAlloc, Fuzzer Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1365073002 Cr-Commit-Position: refs/heads/master@{#30914}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#30913}
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- 17 Sep, 2015 1 commit
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rmcilroy authored
Uncomment the if (!serializer_enabled()) check which I accidentially left commented out after debugging during the CLs development. BUG=chromium:532969 R=bmeurer@chromium.org LOG=n Review URL: https://codereview.chromium.org/1351943002 Cr-Commit-Position: refs/heads/master@{#30811}
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- 14 Sep, 2015 1 commit
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rmcilroy authored
Adds support for JS calls to the interpreter. In order to support calls from the interpreter, the PushArgsAndCall builtin is added which pushes a sequence of arguments onto the stack and calls builtin::Call. Adds the Call bytecode. MIPS port contributed by akos.palfi@imgtec.com in https://codereview.chromium.org/1334873002/ BUG=v8:4280 LOG=N Review URL: https://codereview.chromium.org/1323463005 Cr-Commit-Position: refs/heads/master@{#30710}
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- 03 Sep, 2015 1 commit
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mstarzinger authored
R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1318863004 Cr-Commit-Position: refs/heads/master@{#30554}
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- 20 Aug, 2015 1 commit
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sbonda authored
FlushICache should be NOP for Denver with part numbers 0x0, 0x1 and 0x2 only. Instruction cache needs to flushed for future versions of denver. Review URL: https://codereview.chromium.org/1287173004 Cr-Commit-Position: refs/heads/master@{#30262}
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- 17 Aug, 2015 1 commit
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mstarzinger authored
R=yangguo@chromium.org Review URL: https://codereview.chromium.org/1299563003 Cr-Commit-Position: refs/heads/master@{#30187}
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- 12 Aug, 2015 2 commits
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jfb authored
The operations were available on ARM64 and x86-32 but were unused. It has been conjectured that nontemporals can be used for rowhammer-like bitflips more easily than regular load/store operations. It is therefore desirable to avoid generating these instructions in the future. R= titzer, jochen, jln, Mark Seaborn, ruiq Review URL: https://codereview.chromium.org/1276113002 Cr-Commit-Position: refs/heads/master@{#30139}
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mstarzinger authored
R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1283183002 Cr-Commit-Position: refs/heads/master@{#30127}
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- 15 Jul, 2015 1 commit
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yangguo authored
By not having to patch the return sequence (we patch the debug break slot right before it), we don't overwrite it and therefore don't have to keep the original copy of the code around. R=ulan@chromium.org BUG=v8:4269 LOG=N Review URL: https://codereview.chromium.org/1234833003 Cr-Commit-Position: refs/heads/master@{#29672}
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- 14 Jul, 2015 1 commit
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yangguo authored
The new implemtation counts the number of calls (or continuations) before the PC to find the corresponding PC in the new code. R=mstarzinger@chromium.org BUG=chromium:507070 LOG=N Review URL: https://codereview.chromium.org/1235603002 Cr-Commit-Position: refs/heads/master@{#29636}
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- 13 Jul, 2015 1 commit
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yangguo authored
- split relocation info for debug break slots for - calls (with call arguments count as data) - construct calls - normal slots - renamed DEBUG_BREAK into DEBUGGER_STATEMENT - removed unused IC state for Debug stubs R=ulan@chromium.org BUG=v8:4269 LOG=N Review URL: https://codereview.chromium.org/1232803002 Cr-Commit-Position: refs/heads/master@{#29603}
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- 04 Jun, 2015 1 commit
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mbrandy authored
Embed constant pools within their corresponding Code objects. This removes support for out-of-line constant pools in favor of the new approach -- the main advantage being that it eliminates the need to allocate and manage separate constant pool array objects. Currently supported on PPC and ARM. Enabled by default on PPC only. This yields a 6% improvment in Octane on PPC64. R=bmeurer@chromium.org, rmcilroy@chromium.org, michael_dawson@ca.ibm.com BUG=chromium:478811 LOG=Y Review URL: https://codereview.chromium.org/1162993006 Cr-Commit-Position: refs/heads/master@{#28801}
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- 03 Jun, 2015 1 commit
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bmeurer authored
Revert of Embedded constant pools. (patchset #12 id:220001 of https://codereview.chromium.org/1131783003/) Reason for revert: Breaks Linux nosnap cctest/test-api/FastReturnValuesWithProfiler, see http://build.chromium.org/p/client.v8/builders/V8%20Linux%20-%20nosnap%20-%20debug%20-%202/builds/609/steps/Check/logs/FastReturnValuesWithP.. Original issue's description: > Add support for Embedded Constant Pools for PPC and Arm > > Embed constant pools within their corresponding Code > objects. > > This removes support for out-of-line constant pools in favor > of the new approach -- the main advantage being that it > eliminates the need to allocate and manage separate constant > pool array objects. > > Currently supported on PPC and ARM. Enabled by default on > PPC only. > > This yields a 6% improvment in Octane on PPC64. > > R=danno@chromium.org, svenpanne@chromium.org, bmeurer@chromium.org, rmcilroy@chromium.org, dstence@us.ibm.com, michael_dawson@ca.ibm.com > BUG=chromium:478811 > LOG=Y > > Committed: https://crrev.com/a9404029343d65f146e3443f5280c40a97e736af > Cr-Commit-Position: refs/heads/master@{#28770} TBR=rmcilroy@chromium.org,ishell@chromium.org,rodolph.perfetta@arm.com,mbrandy@us.ibm.com NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=chromium:478811 Review URL: https://codereview.chromium.org/1155703006 Cr-Commit-Position: refs/heads/master@{#28772}
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- 02 Jun, 2015 1 commit
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mbrandy authored
Embed constant pools within their corresponding Code objects. This removes support for out-of-line constant pools in favor of the new approach -- the main advantage being that it eliminates the need to allocate and manage separate constant pool array objects. Currently supported on PPC and ARM. Enabled by default on PPC only. This yields a 6% improvment in Octane on PPC64. R=danno@chromium.org, svenpanne@chromium.org, bmeurer@chromium.org, rmcilroy@chromium.org, dstence@us.ibm.com, michael_dawson@ca.ibm.com BUG=chromium:478811 LOG=Y Review URL: https://codereview.chromium.org/1131783003 Cr-Commit-Position: refs/heads/master@{#28770}
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- 01 Jun, 2015 1 commit
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erikcorry authored
When compiling on a laptop I like to concatenate the small test files. This makes a big difference to compile times. These changes make that easier. R=ulan@chromium.org BUG= Review URL: https://codereview.chromium.org/1163803002 Cr-Commit-Position: refs/heads/master@{#28742}
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- 20 May, 2015 1 commit
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jacob.bramley authored
These trigger warnings on cross-builds under GCC. BUG= Review URL: https://codereview.chromium.org/1151463002 Cr-Commit-Position: refs/heads/master@{#28509}
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- 15 May, 2015 1 commit
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martyn.capewell authored
Enable clang's shorten-64-to-32 warning flag on ARM64, and fix the warnings that arise. BUG= Review URL: https://codereview.chromium.org/1131573006 Cr-Commit-Position: refs/heads/master@{#28412}
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- 19 Mar, 2015 1 commit
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rodolph.perfetta authored
BUG= Review URL: https://codereview.chromium.org/1016073002 Cr-Commit-Position: refs/heads/master@{#27296}
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- 04 Mar, 2015 1 commit
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yangguo authored
We now have BreakLocation::Iterator to iterate via RelocIterator, and create a BreakLocation when we are done iterating. The reloc info is stored in BreakLocation in a GC-safe way and instantiated on demand. R=ulan@chromium.org BUG=v8:3924 LOG=N Review URL: https://codereview.chromium.org/967323002 Cr-Commit-Position: refs/heads/master@{#26983}
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- 13 Feb, 2015 1 commit
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loislo authored
BUG=none LOG=n Review URL: https://codereview.chromium.org/922153002 Cr-Commit-Position: refs/heads/master@{#26639}
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- 12 Feb, 2015 4 commits
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loislo authored
1) create beefy RelocInfo table when cpu profiler is active, so if a function was optimized when profiler was active RelocInfo would get separate DeoptInfo for the each deopt case. 2) push DeoptInfo from CodeEntry to ProfileNode. When deopt happens we put the info collected on #1 into CodeEntry and record stack sample. On the sampling thread we grab the deopt data and append it to the corresponding ProfileNode deopts list. Sample profile dump. [Top down]: 0 (root) 0 #1 1 29 #2 1 test 29 #3 2 opt_function 29 #4 2 opt_function 29 #5 deopted at 118 with reason 'not a heap number' deopted at 137 with reason 'division by zero' BUG=452067 LOG=n Committed: https://crrev.com/ce8701b247d3c6604f24f17a90c02d17b4417f54 Cr-Commit-Position: refs/heads/master@{#26615} Review URL: https://codereview.chromium.org/919953002 Cr-Commit-Position: refs/heads/master@{#26630}
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loislo authored
Revert of CPUProfiler: Push deopt reason further to ProfileNode. (patchset #1 id:1 of https://codereview.chromium.org/919953002/) Reason for revert: static initializers broke the build Original issue's description: > CPUProfiler: Push deopt reason further to ProfileNode. > > 1) create beefy RelocInfo table when cpu profiler is active, so if a function > was optimized when profiler was active RelocInfo would get separate DeoptInfo > for the each deopt case. > > 2) push DeoptInfo from CodeEntry to ProfileNode. > When deopt happens we put the info collected on #1 into CodeEntry and record stack sample. > On the sampling thread we grab the deopt data and append it to the corresponding ProfileNode deopts list. > > Sample profile dump. > [Top down]: > 0 (root) 0 #1 > 1 29 #2 > 5 test 29 #3 > 3 opt_function 29 #4 > deopted at 52 with reason 'not a heap number' > deopted at 71 with reason 'division by zero' > > BUG=452067 > LOG=n > > Committed: https://crrev.com/ce8701b247d3c6604f24f17a90c02d17b4417f54 > Cr-Commit-Position: refs/heads/master@{#26615} TBR=jarin@chromium.org,svenpanne@chromium.org,yurys@chromium.org,alph@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=452067 Review URL: https://codereview.chromium.org/915173005 Cr-Commit-Position: refs/heads/master@{#26616}
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loislo authored
1) create beefy RelocInfo table when cpu profiler is active, so if a function was optimized when profiler was active RelocInfo would get separate DeoptInfo for the each deopt case. 2) push DeoptInfo from CodeEntry to ProfileNode. When deopt happens we put the info collected on #1 into CodeEntry and record stack sample. On the sampling thread we grab the deopt data and append it to the corresponding ProfileNode deopts list. Sample profile dump. [Top down]: 0 (root) 0 #1 1 29 #2 5 test 29 #3 3 opt_function 29 #4 deopted at 52 with reason 'not a heap number' deopted at 71 with reason 'division by zero' BUG=452067 LOG=n Review URL: https://codereview.chromium.org/919953002 Cr-Commit-Position: refs/heads/master@{#26615}
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danno authored
Previously, emitting two more more unique source positions at the same pc would generate two or more RelocInfo entries. Now, only the last emitted source position for any pc is added to the RelocInfo. Review URL: https://codereview.chromium.org/908443002 Cr-Commit-Position: refs/heads/master@{#26608}
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- 11 Feb, 2015 1 commit
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loislo authored
The offensive cl is https://codereview.chromium.org/874323003/ Test: ./out/arm64.debug/d8 --test --random-seed=-235865360 --turbo-deoptimization --turbo-filter=* --always-opt --debug-code --verify-heap --gc-interval=500 --stress-compaction test/mjsunit/mjsunit.js test/mjsunit/regress/regress-builtinbust-7.js --trace-deopt BUG=452067 TBR=dcarney, svenpanne LOG=n Review URL: https://codereview.chromium.org/917823002 Cr-Commit-Position: refs/heads/master@{#26593}
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- 05 Feb, 2015 3 commits
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loislo authored
1) The hardcoded strings were converted into DeoptReason enum. 2) Deopt comment were converted into a pair location and deopt reason entries so the deopt reason tracking mode would less affect the size of the RelocInfo table and heap. 3) DeoptReason entry in RelocInfo reuses kCommentTag value and generates short entry in RelocInfo table. BUG=452067 LOG=n Committed: https://crrev.com/c49820e45b57f128a98690940875c049f612dde6 Cr-Commit-Position: refs/heads/master@{#26434} Committed: https://crrev.com/ec42e002da03adb2db968dd5b7453341ddc59a5c Cr-Commit-Position: refs/heads/master@{#26448} Review URL: https://codereview.chromium.org/874323003 Cr-Commit-Position: refs/heads/master@{#26463}
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bmeurer authored
Revert of Externalize deoptimization reasons. (patchset #7 id:120001 of https://codereview.chromium.org/874323003/) Reason for revert: This CL breaks RelocInfo::INTERNAL_REFERENCE (and maybe others that come after DEOPT_REASON), which is currently (mostly) unused on tip-of-tree, but will be used for jump tables soon(ish) and should therefore work. It seems to be a problem with implicitly assumptions about the number of reloc info modes. Needs further investigation. Original issue's description: > Externalize deoptimization reasons. > > 1) The hardcoded strings were converted into DeoptReason enum. > > 2) Deopt comment were converted into a pair location and deopt reason entries so > the deopt reason tracking mode would less affect the size of the RelocInfo table and heap. > > 3) DeoptReason entry in RelocInfo reuses kCommentTag value and generates short entry in RelocInfo table. > > BUG=452067 > LOG=n > > Committed: https://crrev.com/c49820e45b57f128a98690940875c049f612dde6 > Cr-Commit-Position: refs/heads/master@{#26434} > > Committed: https://crrev.com/ec42e002da03adb2db968dd5b7453341ddc59a5c > Cr-Commit-Position: refs/heads/master@{#26448} TBR=alph@chromium.org,mstarzinger@chromium.org,svenpanne@chromium.org,yurys@chromium.org,loislo@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=452067 Review URL: https://codereview.chromium.org/900223002 Cr-Commit-Position: refs/heads/master@{#26457}
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loislo authored
1) The hardcoded strings were converted into DeoptReason enum. 2) Deopt comment were converted into a pair location and deopt reason entries so the deopt reason tracking mode would less affect the size of the RelocInfo table and heap. 3) DeoptReason entry in RelocInfo reuses kCommentTag value and generates short entry in RelocInfo table. BUG=452067 LOG=n Committed: https://crrev.com/c49820e45b57f128a98690940875c049f612dde6 Cr-Commit-Position: refs/heads/master@{#26434} Review URL: https://codereview.chromium.org/874323003 Cr-Commit-Position: refs/heads/master@{#26448}
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- 04 Feb, 2015 2 commits
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loislo authored
Revert of Externalize deoptimization reasons. (patchset #6 id:100001 of https://codereview.chromium.org/874323003/) Reason for revert: it broke the build Original issue's description: > Externalize deoptimization reasons. > > 1) The hardcoded strings were converted into DeoptReason enum. > > 2) Deopt comment were converted into a pair location and deopt reason entries so > the deopt reason tracking mode would less affect the size of the RelocInfo table and heap. > > 3) DeoptReason entry in RelocInfo reuses kCommentTag value and generates short entry in RelocInfo table. > > BUG=452067 > LOG=n > > Committed: https://crrev.com/c49820e45b57f128a98690940875c049f612dde6 > Cr-Commit-Position: refs/heads/master@{#26434} TBR=alph@chromium.org,mstarzinger@chromium.org,svenpanne@chromium.org,yurys@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=452067 Review URL: https://codereview.chromium.org/892843007 Cr-Commit-Position: refs/heads/master@{#26435}
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loislo authored
1) The hardcoded strings were converted into DeoptReason enum. 2) Deopt comment were converted into a pair location and deopt reason entries so the deopt reason tracking mode would less affect the size of the RelocInfo table and heap. 3) DeoptReason entry in RelocInfo reuses kCommentTag value and generates short entry in RelocInfo table. BUG=452067 LOG=n Review URL: https://codereview.chromium.org/874323003 Cr-Commit-Position: refs/heads/master@{#26434}
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- 19 Dec, 2014 1 commit
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arajp authored
Denver supports a coherent cache mechanism. There is no need to clean the D cache and invalidate I cache. MTS has to check the translation anytime there is an I cache invalidate and this time can be saved by making FlushICache a NOP. The patch improves Octane by roughly 3-4% on Denver. Review URL: https://codereview.chromium.org/797233002 Cr-Commit-Position: refs/heads/master@{#25898}
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- 16 Dec, 2014 2 commits
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erikcorry authored
R=ulan@chromium.org BUG= Review URL: https://codereview.chromium.org/810473004 Cr-Commit-Position: refs/heads/master@{#25852}
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erik.corry authored
R=jkummerow@chromium.org BUG= Review URL: https://codereview.chromium.org/812593002 Cr-Commit-Position: refs/heads/master@{#25848}
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- 07 Nov, 2014 1 commit
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rmcilroy@chromium.org authored
Remove the forced alignment of csp to 16 byte values on Nvidia chips. Benchmarks on current devices show that this is no longer required. R=rodolph.perfetta@arm.com, ulan@chromium.org Review URL: https://codereview.chromium.org/710613002 Cr-Commit-Position: refs/heads/master@{#25225} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25225 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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