1. 02 Aug, 2017 3 commits
  2. 01 Aug, 2017 2 commits
  3. 28 Jul, 2017 2 commits
    • Juliana Patricia Vicente Franco's avatar
      Revert "Changing the return address on the stack." · a193fde9
      Juliana Patricia Vicente Franco authored
      This reverts commit e15f5544.
      
      Reason for revert: it breaks the GC stress. 
      
      Original change's description:
      > Changing the return address on the stack.
      > 
      > Rather than patching code, the deoptimizer now replaces the
      > return address in the frames with respective trampolines. 
      > This change required to change the way we search for Safepoint 
      > entries and for Exception Handlers. 
      > It's working in architectures: x64, ia32, arm, arm64 and mips. 
      > 
      > Bug: V8:6563
      > Change-Id: I3cbd4d192c3513f307b3a6a2ac99e60d03c753d3
      > Reviewed-on: https://chromium-review.googlesource.com/586707
      > Commit-Queue: Juliana Patricia Vicente Franco <jupvfranco@google.com>
      > Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
      > Cr-Commit-Position: refs/heads/master@{#46967}
      
      TBR=jarin@chromium.org,bmeurer@chromium.org,jupvfranco@google.com
      
      Change-Id: I430fa9123beef2e0723b38cdef9537181203f7e7
      No-Presubmit: true
      No-Tree-Checks: true
      No-Try: true
      Bug: V8:6563
      Reviewed-on: https://chromium-review.googlesource.com/591371
      Commit-Queue: Jaroslav Sevcik <jarin@chromium.org>
      Reviewed-by: 's avatarJaroslav Sevcik <jarin@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#46969}
      a193fde9
    • Juliana Franco's avatar
      Changing the return address on the stack. · e15f5544
      Juliana Franco authored
      Rather than patching code, the deoptimizer now replaces the
      return address in the frames with respective trampolines. 
      This change required to change the way we search for Safepoint 
      entries and for Exception Handlers. 
      It's working in architectures: x64, ia32, arm, arm64 and mips. 
      
      Bug: V8:6563
      Change-Id: I3cbd4d192c3513f307b3a6a2ac99e60d03c753d3
      Reviewed-on: https://chromium-review.googlesource.com/586707
      Commit-Queue: Juliana Patricia Vicente Franco <jupvfranco@google.com>
      Reviewed-by: 's avatarJaroslav Sevcik <jarin@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#46967}
      e15f5544
  4. 26 Jul, 2017 1 commit
  5. 24 Jul, 2017 1 commit
  6. 20 Jul, 2017 2 commits
  7. 17 Jul, 2017 1 commit
  8. 14 Jul, 2017 1 commit
  9. 13 Jul, 2017 2 commits
  10. 12 Jul, 2017 1 commit
  11. 11 Jul, 2017 1 commit
  12. 10 Jul, 2017 3 commits
  13. 07 Jul, 2017 1 commit
  14. 03 Jul, 2017 1 commit
  15. 28 Jun, 2017 1 commit
  16. 27 Jun, 2017 1 commit
  17. 20 Jun, 2017 1 commit
  18. 19 Jun, 2017 1 commit
  19. 12 Jun, 2017 1 commit
  20. 08 Jun, 2017 1 commit
    • bbudge's avatar
      [WASM] Eliminate SIMD boolean vector types. · 381f7da0
      bbudge authored
      - Eliminates b1x4, b1x8, and b1x16 as distinct WASM types.
      - All vector comparisons return v128 type.
      - Eliminates b1xN and, or, xor, not.
      - Selects take a v128 mask vector and are now bit-wise.
      - Adds a new test for Select, where mask is non-canonical (not 0's and -1's).
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2919203002
      Cr-Commit-Position: refs/heads/master@{#45795}
      381f7da0
  21. 05 Jun, 2017 1 commit
  22. 01 Jun, 2017 1 commit
  23. 24 May, 2017 1 commit
    • dusan.simicic's avatar
      MIPS[64]: Support for some SIMD operations (7) · a8421ddd
      dusan.simicic authored
      Add support for I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS,
      I8x16Mul, I8x16MaxS, I8x16MinS, I8x16Eq, I8x16Ne, I8x16LtS,
      I8x16LeS, I8x16ShrU, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MaxU,
      I8x16MinU, I8x16LtU, I8x16LeU, S128And, S128Or, S128Xor, S128Not for
      mips32 and mips64 architectures.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2798853003
      Cr-Commit-Position: refs/heads/master@{#45512}
      a8421ddd
  24. 22 May, 2017 1 commit
  25. 21 May, 2017 1 commit
    • gdeepti's avatar
      [wasm] Swap the implementation of SIMD compare ops using Gt/Ge insteas of Lt/Le · eeefc74a
      gdeepti authored
      Currently SIMD integer comparison ops are implemented using Lt/Le, this is
      sub-optimal on Intel, because all compares are done using pcmpgt(d/w/b) that
      clobber the destination register, and will need additional instructions to
      when using Lt/Le as the base implementation. This CL proposes moving to Gt/Ge
      as the underlying implementation as this will only require swapping operands
      on MIPS and is consistent with x86/ARM instructions.
      
      BUG=v8:6020
      
      R=bbudge@chromium.org, bmeurer@chromium.org, bradnelson@chromium.org
      
      Review-Url: https://codereview.chromium.org/2874403002
      Cr-Commit-Position: refs/heads/master@{#45440}
      eeefc74a
  26. 16 May, 2017 1 commit
  27. 15 May, 2017 1 commit
    • dusan.simicic's avatar
      MIPS[64]: Support for some SIMD operations (6) · b99a1ba0
      dusan.simicic authored
      Add support for I16x8Mul, I16x8MaxS, I16x8MinS, I16x8Eq, I16x8Ne,
      I16x8LtS, I16x8LeS, I16x8AddSaturateU, I16x8SubSaturateU, I16x8MaxU,
      I16x8MinU, I16x8LtU, I16x8LeU, I8x16Splat, I8x16ExtractLane,
      I8x16ReplaceLane, I8x16Neg, I8x16Shl, I8x16ShrS, S16x8Select,
      S8x16Select for mips32 and mips64 architectures.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2791213003
      Cr-Commit-Position: refs/heads/master@{#45312}
      b99a1ba0
  28. 12 May, 2017 1 commit
  29. 10 May, 2017 1 commit
  30. 09 May, 2017 2 commits
  31. 04 May, 2017 1 commit