1. 14 Apr, 2018 1 commit
    • Jakob Kummerow's avatar
      [ubsan] Change Address typedef to uintptr_t · 2459046c
      Jakob Kummerow authored
      The "Address" type is V8's general-purpose type for manipulating memory
      addresses. Per the C++ spec, pointer arithmetic and pointer comparisons
      are undefined behavior except within the same array; since we generally
      don't operate within a C++ array, our general-purpose type shouldn't be
      a pointer type.
      
      Bug: v8:3770
      Cq-Include-Trybots: luci.chromium.try:linux_chromium_rel_ng;master.tryserver.blink:linux_trusty_blink_rel
      Change-Id: Ib96016c24a0f18bcdba916dabd83e3f24a1b5779
      Reviewed-on: https://chromium-review.googlesource.com/988657
      Commit-Queue: Jakob Kummerow <jkummerow@chromium.org>
      Reviewed-by: 's avatarLeszek Swirski <leszeks@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#52601}
      2459046c
  2. 09 Feb, 2018 1 commit
  3. 12 Jan, 2018 1 commit
  4. 09 Jan, 2018 1 commit
  5. 08 Jan, 2018 1 commit
    • Clemens Hammacher's avatar
      [simulator] Make Call variadic · a3baa353
      Clemens Hammacher authored
      In order to remove the CALL_GENERATED_CODE macro, it helps a lot to
      unify the interfaces of the simulators and make the Call method variadic
      in the number of arguments.
      This CL does that for each simulator. A follow-up CL will then
      completely remove the CALL_GENERATED_CODE macro and replace uses with
      the (new) GeneratedCode wrapper.
      
      R=mstarzinger@chromium.org
      
      Bug: v8:7182
      Change-Id: I1f81445ec2faba30f0bd233b022ae1f0fae4e96f
      Reviewed-on: https://chromium-review.googlesource.com/850873
      Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
      Reviewed-by: 's avatarMichael Starzinger <mstarzinger@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#50413}
      a3baa353
  6. 15 Dec, 2017 1 commit
  7. 13 Dec, 2017 1 commit
    • Michael Starzinger's avatar
      [simulator] Refactor redirections to be process-wide. · f4dde200
      Michael Starzinger authored
      This refactors the list of redirections of runtime call targets that
      simulators maintain to be process-wide (as opposed to be per Isolate).
      Such redirections are used for static C++ call targets which themselves
      are process-wide, which makes this model a closer fit. Access is already
      properly synchronized via a mutex.
      
      Along the way this also introduces the {SimulatorBase} class as a common
      base class for all simulator implementations.
      
      R=clemensh@chromium.org
      
      Change-Id: Iae8602c44b1b34cb916dde2b22c9403b0496b3d4
      Reviewed-on: https://chromium-review.googlesource.com/823966
      Commit-Queue: Michael Starzinger <mstarzinger@chromium.org>
      Reviewed-by: 's avatarClemens Hammacher <clemensh@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#50074}
      f4dde200
  8. 11 Dec, 2017 2 commits
  9. 17 Oct, 2017 1 commit
  10. 02 Aug, 2017 1 commit
  11. 02 May, 2017 1 commit
    • neis's avatar
      [simulator] Make reference redirection thread-safe. · 34e79456
      neis authored
      In the simulators, the ExternalReference constructor rewrites external
      addresses, which involves mutating a linked list rooted in the isolate.
      
      We already construct external references concurrently (at least in Turbofan),
      but the list mutation was not thread-safe (though no crashes are known). This
      CL adds the necessary locking.
      
      BUG=v8:6048
      
      Review-Url: https://codereview.chromium.org/2852983002
      Cr-Commit-Position: refs/heads/master@{#45014}
      34e79456
  12. 21 Apr, 2017 5 commits
  13. 10 Apr, 2017 3 commits
  14. 02 Mar, 2017 1 commit
    • bbudge's avatar
      Implement remaining Boolean SIMD operations on ARM. · 386e5a11
      bbudge authored
      - Implements Select instructions using a single ARM vbsl instruction.
      - Renames boolean machine operators to match renamed S1xN machine types.
      - Implements S1xN vector logical ops, AND, OR, XOR, NOT for ARM.
      - Implements S1xN AnyTrue, AllTrue ops for ARM.
      - Eliminates unused SIMD op categories in opcodes.h.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2711863002
      Cr-Commit-Position: refs/heads/master@{#43556}
      386e5a11
  15. 18 Jan, 2017 1 commit
    • binji's avatar
      Implement ldrex/strex instructions in ARM simulator · 66ae5f7d
      binji authored
      This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
      Simulator. These instructions provide "exclusive" access, which provides mutual
      exclusion for concurrent threads of execution.
      
      The ARM specification gives some leeway to implementors, but essentially
      describes each processor as having Local Monitor and Global Monitor. The Local
      Monitor is used to check the exclusivity state without having to synchronize
      with other processors. The Global Monitor is shared between processors. We
      model both to make it easier to match behavior with the spec.
      
      When running with multiple OS threads, each thread has its own isolate, and
      each isolate has its own Simulator. The Local Monitor is stored directly on the
      Simulator, and the Global Monitor is stored as a lazy singleton. The Global
      Monitor maintains a linked-list of all Simulators.
      
      All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
      
      BUG=v8:4614
      
      Review-Url: https://codereview.chromium.org/2006183004
      Cr-Commit-Position: refs/heads/master@{#42481}
      66ae5f7d
  16. 09 Jan, 2017 1 commit
  17. 15 Dec, 2016 1 commit
  18. 30 Sep, 2016 1 commit
  19. 06 Sep, 2016 1 commit
  20. 09 Jun, 2016 1 commit
    • lpy's avatar
      Move hashmap into src/base. · 2fd55667
      lpy authored
      We ported hashmap.h into libsampler as a workaround before, so the main focus of
      this patch is to reduce code duplication. This patch moves the hashmap into
      src/base as well as creates DefaultAllocationPolicy using malloc and free.
      
      BUG=v8:5050
      LOG=n
      
      Review-Url: https://codereview.chromium.org/2010243003
      Cr-Commit-Position: refs/heads/master@{#36873}
      2fd55667
  21. 16 Mar, 2016 1 commit
    • ahaas's avatar
      [wasm] Int64Lowering of Int64Sub on ia32 and arm. · 33c08596
      ahaas authored
      Int64Sub is lowered to a new turbofan operator, Int32SubPair. The new
      operator takes 4 inputs an generates 2 outputs. The inputs are the low
      word of the left input, high word of the left input, the low word of the
      right input, and high word of the right input. The ouputs are the low
      and high word of the result of the subtraction.
      
      The implementation is very similar to the implementation of Int64Add.
      
      @v8-arm-ports: please take a careful look at the implementation of sbc
      in the simulator.
      
      R=titzer@chromium.org, v8-arm-ports@googlegroups.com
      
      Review URL: https://codereview.chromium.org/1778893005
      
      Cr-Commit-Position: refs/heads/master@{#34808}
      33c08596
  22. 10 Mar, 2016 1 commit
  23. 23 Nov, 2015 1 commit
  24. 30 Sep, 2015 1 commit
  25. 24 Aug, 2015 1 commit
  26. 20 May, 2015 1 commit
    • svenpanne's avatar
      Fixed various simulator-related space leaks. · 84aa494e
      svenpanne authored
      Alas, this involved quite a bit of copy-n-paste between the
      architectures, but this is caused by the very convoluted
      relationships, lifetimes and distribution of responsibilities. This
      should really be cleaned up by moving code around and using STL maps,
      but that's not really a priority right now.
      
      Bonus: Fixed leaks in the ARM64 disassembler tests.
      
      Review URL: https://codereview.chromium.org/1132943007
      
      Cr-Commit-Position: refs/heads/master@{#28496}
      84aa494e
  27. 30 Mar, 2015 1 commit
    • bmeurer's avatar
      [turbofan] Add backend support for float32 operations. · 8dad78cd
      bmeurer authored
      This adds the basics necessary to support float32 operations in TurboFan.
      The actual functionality required to detect safe float32 operations will
      be added based on this later. Therefore this does not affect production
      code except for some cleanup/refactoring.
      
      In detail, this patchset contains the following features:
      - Add support for float32 operations to arm, arm64, ia32 and x64
        backends.
      - Add float32 machine operators.
      - Add support for float32 constants to simplified lowering.
      - Handle float32 representation for phis in simplified lowering.
      
      In addition, contains the following (related) cleanups:
      - Fix/unify naming of backend instructions.
      - Use AVX comparisons when available.
      - Extend ArchOpcodeField to 9 bits (required for arm64).
      - Refactor some code duplication in instruction selectors.
      
      BUG=v8:3589
      LOG=n
      R=dcarney@chromium.org
      
      Review URL: https://codereview.chromium.org/1044793002
      
      Cr-Commit-Position: refs/heads/master@{#27509}
      8dad78cd
  28. 20 Jun, 2014 1 commit
  29. 03 Jun, 2014 1 commit
  30. 20 May, 2014 1 commit
  31. 09 May, 2014 1 commit
  32. 29 Apr, 2014 1 commit
  33. 12 Feb, 2014 1 commit