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    • arajp's avatar
      Make FlushICache NOP for Nvidia Denver CPU's. · f4fb7025
      arajp authored
      Denver supports a coherent cache mechanism. There is no need to clean
      the D cache and invalidate I cache. MTS has to check the translation
      anytime there is an I cache invalidate and this time can be saved by
      making FlushICache a NOP.
      
      The patch improves Octane by roughly 3-4% on Denver.
      
      Review URL: https://codereview.chromium.org/797233002
      
      Cr-Commit-Position: refs/heads/master@{#25898}
      f4fb7025
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    • rmcilroy@chromium.org's avatar
      Arm64: Ensure that csp is always aligned to 16 byte values even if jssp is not. · 53bf1268
      rmcilroy@chromium.org authored
      Even although the Arm64 specification specifies that csp
      only needs to be aligned to 16 bytes if it is dereferenced, some implementations show poor performance if csp is every set to a non-aligned value.  This CL ensures that csp is always aligned to 16 byte values on these platforms and adds checks to ensure this in debug mode.
      
      Also makes the following change:
       - Enable CPU support for arm64 to enable probing of cpu implementer and cpu part.
       - Add ALWAYS_ALIGN_CSP CpuFeature for Arm64 and set it based on runtime probing of the cpu implementer.
       - Rename PrepareForPush and PrepareForPop to PushPreamble and PopPostamble and move PopPostable after the pop.
       -
      
      R=jacob.bramley@arm.com, ulan@chromium.org
      
      Review URL: https://codereview.chromium.org/264773004
      
      git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21177 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      53bf1268
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