Change-Id: Ic1130d1bba3f70906cd39685bfa45b214424c2e3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2644952
Auto-Submit: Jakob Kummerow <jkummerow@chromium.org>
Commit-Queue: Michael Lippautz <mlippautz@chromium.org>
Reviewed-by: Michael Lippautz <mlippautz@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72271}

- Add the appropriate cpuid checks to detect AVX2 in base/cpu
- Add FLAG_enable_avx2

AVX2 depends on AVX support, + a cpuid check with eax=7. This is similar
to chromium/src/base/cpu.cc check for AVX2.

Bug: v8:11258
Change-Id: Ia547c22e51b03fec823f5e48ebb055139632c942
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2589050Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71821}

Mac-arm64 devices always have support for it.
Found by thakis@chromium.org

Change-Id: Id2dd9d53b66715efe8b4f7f0019d1ba06289c359
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2547281Reviewed-by: Michael Lippautz <mlippautz@chromium.org>
Commit-Queue: Michael Lippautz <mlippautz@chromium.org>
Auto-Submit: Jakob Kummerow <jkummerow@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71268}

Bug: v8:10927
Change-Id: Icbdc0d7329ddd466e7d67a954246a35795b4dece
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2507310
Commit-Queue: Ulan Degenbaev <ulan@chromium.org>
Reviewed-by: Peter Marshall <petermarshall@chromium.org>
Reviewed-by: Michael Lippautz <mlippautz@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Toon Verwaest <verwaest@chromium.org>
Reviewed-by: Ulan Degenbaev <ulan@chromium.org>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71220}

Starboard is the platform abstraction for Cobalt.
This CL introduces all Cobalt changes in src/base/platform.

The review was conducted mostly on:
https://chromium-review.googlesource.com/c/v8/v8/+/2247918

See b/156155426 for background

Tbr: mlippautz@chromium.org
Change-Id: I6cd092304ba6485acd38e82aa2dc4505d7dfb0aa
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2346090
Commit-Queue: John Xu <johnx@google.com>
Reviewed-by: Michael Lippautz <mlippautz@chromium.org>
Reviewed-by: Ulan Degenbaev <ulan@chromium.org>
Cr-Commit-Position: refs/heads/master@{#69530}

This includes the instruction opcode, its use in TF, its support in the
simulator and the detection of the associated CPU feature.

The instruction can be tested in the simulator with the new
--sim-arm64-optional-features flag.

Change-Id: I6047fa16696394fe0ced4535f7788d2c8716a18c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2222348Reviewed-by: Ross McIlroy <rmcilroy@chromium.org>
Reviewed-by: Georg Neis <neis@chromium.org>
Commit-Queue: Georg Neis <neis@chromium.org>
Cr-Commit-Position: refs/heads/master@{#68261}

This reverts commit f5bee002.

Reason for revert: Crashes android webview, see https://crbug.com/1071708.

Original change's description:
> Revisiting auxvec data gathering for PPC/ARM.
> 
> /proc/sys/auxv might not be accessible, instead
> getting these from the user's stack.
> 
> Change-Id: I2dcf696734e2b4dc1da27a991930b9e0d4228d51
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1730990
> Commit-Queue: Clemens Backes [né Hammacher] <clemensb@chromium.org>
> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
> Reviewed-by: Clemens Backes [né Hammacher] <clemensb@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#64037}

TBR=clemensb@chromium.org,bmeurer@chromium.org,devnexen@gmail.com

# Not skipping CQ checks because original CL landed > 1 day ago.

Bug: chromium:1071708
Change-Id: I05659f245c1020e98b7225a25e82987d9955d595
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2154800Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#67234}

The same issue has been fixed in Chromium [1] by Richard Townsend.
It seems that cl needs to be applied in V8 as well.

[1] https://chromium-review.googlesource.com/c/chromium/src/+/1593363

Also add self to authors file.

Bug: v8:10365
Change-Id: Ic38b18392263c2a89f207013ec61718418d5f132
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2130126
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66940}

After support for ARCH_PPC was dropped, it became a subset of
ARCH_PPC64. If you compile for ppc64, then you set the ARCH_PPC64
define which also sets the ARCH_PPC define.
To be able to again support ppc (32 bit) those defines should be
split up again.

This commit only splits up the defines but does not introduce a
working ARCH_PPC variant.

Bug: v8:10102
Change-Id: I64e0749f8e5a7dc078ee7890d92e57b82706a849
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1989826
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Peter Marshall <petermarshall@chromium.org>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Reviewed-by: Hannes Payer <hpayer@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Reviewed-by: Milad Farazmand <miladfar@ca.ibm.com>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66390}

Change-Id: I4d4c6e8a6371102ae7b2ece7cbbc068cdd8c6799
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1832165Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64058}

/proc/sys/auxv might not be accessible, instead
getting these from the user's stack.

Change-Id: I2dcf696734e2b4dc1da27a991930b9e0d4228d51
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1730990
Commit-Queue: Clemens Backes [né Hammacher] <clemensb@chromium.org>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Reviewed-by: Clemens Backes [né Hammacher] <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64037}

For mips, if 'mips_arch_variant=="r6"' and if 'mips_use_msa' flag is set
to 'true', then test-run-wasm-simd tests won't be skipped for mips. It
will also force 'MIPS_SIMD' bit in CpuFeatures to be set.
ARM processors are assumed to support SIMD.

Change-Id: Iea668b97ef995ca4949ddbf2ffc734aad89d3aa3
Reviewed-on: https://chromium-review.googlesource.com/868430Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#50981}

This patch normalizes the casing of hexadecimal digits in escape
sequences of the form `\xNN` and integer literals of the form
`0xNNNN`.

Previously, the V8 code base used an inconsistent mixture of uppercase
and lowercase.

Google’s C++ style guide uses uppercase in its examples:
https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters

Moreover, uppercase letters more clearly stand out from the lowercase
`x` (or `u`) characters at the start, as well as lowercase letters
elsewhere in strings.

BUG=v8:7109
TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org
NOPRESUBMIT=true

Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng
Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6
Reviewed-on: https://chromium-review.googlesource.com/804294
Commit-Queue: Mathias Bynens <mathias@chromium.org>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49810}

This CL fixes all occurences that don't require special OWNER reviews,
or can be reviewed by Michi.

After this one, we should be able to reenable the readability/check
cpplint check.

R=mstarzinger@chromium.org

Bug: v8:6837, v8:6921
Cq-Include-Trybots: master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng
Change-Id: Ic81d68d5534eaa795b7197fed5c41ed158361d62
Reviewed-on: https://chromium-review.googlesource.com/721120
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#48670}

New code should use nullptr instead of NULL.

This patch updates existing use of NULL to nullptr where applicable,
making the code base more consistent.

BUG=v8:6928,v8:6921

Cq-Include-Trybots: master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng
Change-Id: I4687f5b96fcfd88b41fa970a2b937b4f6538777c
Reviewed-on: https://chromium-review.googlesource.com/718338
Commit-Queue: Mathias Bynens <mathias@chromium.org>
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Reviewed-by: Ulan Degenbaev <ulan@chromium.org>
Reviewed-by: Toon Verwaest <verwaest@chromium.org>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Yang Guo <yangguo@chromium.org>
Cr-Commit-Position: refs/heads/master@{#48557}

There are currently no decisions based on the CPU implementor, variant
or part values for ARM64, and the code to fetch those values was not
compatible with Fuchsia/ARM64.

Bug: chromium:772031
Change-Id: I2305fc7a97d8c0a24bb0ad115447665976e5814a
Reviewed-on: https://chromium-review.googlesource.com/706642Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Reviewed-by: Rodolph Perfetta <rodolph.perfetta@arm.com>
Commit-Queue: Wez <wez@chromium.org>
Cr-Commit-Position: refs/heads/master@{#48472}

Bug: chromium:750830
Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng
Change-Id: Icab7b5a1c469d5e77d04df8bfca8319784e92af4
Reviewed-on: https://chromium-review.googlesource.com/595655
Commit-Queue: Julien Brianceau <jbriance@cisco.com>
Reviewed-by: Yang Guo <yangguo@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: Daniel Ehrenberg <littledan@chromium.org>
Cr-Commit-Position: refs/heads/master@{#47072}

This patch adds support for MIPS SIMD (MSA) instructions in Assembler
and Decoder (disassembler) classes. MSA instructions are implemented for
both mips32 and mips64 architectures.

BUG=

Review-Url: https://codereview.chromium.org/2740123004
Cr-Commit-Position: refs/heads/master@{#44148}

Power9 support was originally added in CL
https://codereview.chromium.org/2625013002

R=jochen@chromium.org
BUG=
LOG=N

Review-Url: https://codereview.chromium.org/2637213002
Cr-Commit-Position: refs/heads/master@{#42458}

Enabled support for Power9 hardware and implemented P9 modulo
instruction.

R=joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, jochen@chromium.org
BUG=
LOG=n

Review-Url: https://codereview.chromium.org/2625013002
Cr-Commit-Position: refs/heads/master@{#42341}

Review-Url: https://codereview.chromium.org/2491373003
Cr-Commit-Position: refs/heads/master@{#40940}

BUG=v8:5614

Review-Url: https://codereview.chromium.org/2493553002
Cr-Commit-Position: refs/heads/master@{#40892}

Review-Url: https://codereview.chromium.org/2175193003
Cr-Commit-Position: refs/heads/master@{#38081}

We already implemented CPU time for OS X and POSIX, this path is a
follow up for the implementation on Windows.

BUG=v8:5000
LOG=n

Review-Url: https://codereview.chromium.org/1977983003
Cr-Commit-Position: refs/heads/master@{#36656}

AArch64 kernels older than 3.18 presented a different cpuinfo format
than what V8 expects. Most of V8's logic still works, but it misreads
the "CPU architecture" field.

BUG=

Review URL: https://codereview.chromium.org/1841733002

Cr-Commit-Position: refs/heads/master@{#35114}

This version does not modify arm64.

R=jkummerow@chromium.org, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1806893002

Cr-Commit-Position: refs/heads/master@{#34827}

along with "[arm64] Fix i/d cache line size confusion typo"
and "Fix a warning about inline asm source/destination mismatches..."
which were building on it.

This reverts the following commits:
8d7399f9
474e6a3d
c3ff68b6

Reason for revert: We're getting a large number of crash reports from
arm64 devices that are obviously related to cache flushing after code
patching. Bisection results say that the problems started at revision
c3ff68b6. Since I can't find a bug in that CL except for the typo that
I've fixed in 474e6a3d (which made some of the crashes go away but not
all of them), we have no choice but to revert the changes in order to
get stability under control while we investigate.

BUG=chromium:594646
LOG=n

Review URL: https://codereview.chromium.org/1806853002

Cr-Commit-Position: refs/heads/master@{#34816}

The warning notes that we'd want a 'w' register here because the size of
the operand is 32-bit, however, the instruction only takes an 'x'
register and so force that using the 'x' modifier on the instruction.

BUG=

Review URL: https://codereview.chromium.org/1799263002

Cr-Commit-Position: refs/heads/master@{#34766}

BUG=chromium:593867
LOG=y

Review URL: https://codereview.chromium.org/1783343002

Cr-Commit-Position: refs/heads/master@{#34719}

In the interest of generalization, this change:
- Consolidates cache line size detection for all interested
  architectures under base::CPU (currently leveraged by only
  PPC and ARM64).
- Differentiates between instruction vs data cache line sizes.

R=rmcilroy@chromium.org, jochen@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1643363002

Cr-Commit-Position: refs/heads/master@{#33642}

This enables linter checking for "readability/namespace" violations
during presubmit and instead marks the few known exceptions that we
allow explicitly.

R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1371083003

Cr-Commit-Position: refs/heads/master@{#31019}

R=jochen@chromium.org

Review URL: https://codereview.chromium.org/1088993003

Cr-Commit-Position: refs/heads/master@{#27937}

BUG=v8:4015
LOG=n

Review URL: https://codereview.chromium.org/1040603002

Cr-Commit-Position: refs/heads/master@{#27648}

BUG=

Review URL: https://codereview.chromium.org/998883002

Cr-Commit-Position: refs/heads/master@{#27315}

Contribution of PowerPC port (continuation of 422063005 and 817143002). This patch covers
the key changes needed to the common files needed to support AIX. Subsequent
patches will cover:
- changes to update the ppc directories so they are current with the changes
in the rest of the project.
- remaining AIX changes not resolved by 4.8 compiler
- individual optimizations for PPC

This is based off of the GitHub repository
https://github.com/andrewlow/v8ppc

R=danno@chromium.org, svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/866843003

Cr-Commit-Position: refs/heads/master@{#26343}

BUG=chromium:452033, v8:3846
LOG=y
R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/878063002

Cr-Commit-Position: refs/heads/master@{#26288}

BUG=v8:3844
LOG=y
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/867713003

Patch from Ben Noordhuis <info@bnoordhuis.nl>.

Cr-Commit-Position: refs/heads/master@{#26234}

Review URL: https://codereview.chromium.org/853703002

Cr-Commit-Position: refs/heads/master@{#26163}

Contribution of PowerPC port (continuation of 422063005). The inital patch
covers the core changes to the common files.  Subsequent patches will cover
changes to common files to support AIX and to update the ppc directories so
they are current with the changes in the rest of the project.

This is based off of the GitHub repository
https://github.com/andrewlow/v8ppc

BUG=
R=svenpanne@chromium.org, danno@chromium.org, sevnpanne@chromium.org

Review URL: https://codereview.chromium.org/817143002

Cr-Commit-Position: refs/heads/master@{#26091}

Denver supports a coherent cache mechanism. There is no need to clean
the D cache and invalidate I cache. MTS has to check the translation
anytime there is an I cache invalidate and this time can be saved by
making FlushICache a NOP.

The patch improves Octane by roughly 3-4% on Denver.

Review URL: https://codereview.chromium.org/797233002

Cr-Commit-Position: refs/heads/master@{#25898}