1. 21 Dec, 2017 1 commit
    • Andreas Haas's avatar
      [mips][turbofan] Implement on-stack returns. · 3ede3487
      Andreas Haas authored
      This is the implementation of crrev.com/c/766371 for mips.
      
      Original description:
      
      Add the ability to return (multiple) return values on the stack:
      
      - Extend stack frames with a new buffer region for return slots.
        This region is located at the end of a caller's frame such that
        its slots can be indexed as caller frame slots in a callee
        (located beyond its parameters) and assigned return values.
      - Adjust stack frame constructon and deconstruction accordingly.
      - Extend linkage computation to support register plus stack returns.
      - Reserve return slots in caller frame when respective calls occur.
      - Introduce and generate architecture instructions ('peek') for
        reading back results from return slots in the caller.
      - Aggressive tests.
      - Some minor clean-up.
      
      R=v8-mips-ports@googlegroups.com
      
      Change-Id: I2f30cc297771ec74b0b935b6ea28d3d61a986d5c
      Reviewed-on: https://chromium-review.googlesource.com/839660Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@mips.com>
      Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
      Commit-Queue: Andreas Haas <ahaas@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#50272}
      3ede3487
  2. 28 Jun, 2017 1 commit
  3. 27 Jun, 2017 1 commit
  4. 20 Jun, 2017 1 commit
  5. 08 Jun, 2017 1 commit
    • bbudge's avatar
      [WASM] Eliminate SIMD boolean vector types. · 381f7da0
      bbudge authored
      - Eliminates b1x4, b1x8, and b1x16 as distinct WASM types.
      - All vector comparisons return v128 type.
      - Eliminates b1xN and, or, xor, not.
      - Selects take a v128 mask vector and are now bit-wise.
      - Adds a new test for Select, where mask is non-canonical (not 0's and -1's).
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2919203002
      Cr-Commit-Position: refs/heads/master@{#45795}
      381f7da0
  6. 01 Jun, 2017 1 commit
  7. 24 May, 2017 1 commit
    • dusan.simicic's avatar
      MIPS[64]: Support for some SIMD operations (7) · a8421ddd
      dusan.simicic authored
      Add support for I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS,
      I8x16Mul, I8x16MaxS, I8x16MinS, I8x16Eq, I8x16Ne, I8x16LtS,
      I8x16LeS, I8x16ShrU, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MaxU,
      I8x16MinU, I8x16LtU, I8x16LeU, S128And, S128Or, S128Xor, S128Not for
      mips32 and mips64 architectures.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2798853003
      Cr-Commit-Position: refs/heads/master@{#45512}
      a8421ddd
  8. 21 May, 2017 1 commit
    • gdeepti's avatar
      [wasm] Swap the implementation of SIMD compare ops using Gt/Ge insteas of Lt/Le · eeefc74a
      gdeepti authored
      Currently SIMD integer comparison ops are implemented using Lt/Le, this is
      sub-optimal on Intel, because all compares are done using pcmpgt(d/w/b) that
      clobber the destination register, and will need additional instructions to
      when using Lt/Le as the base implementation. This CL proposes moving to Gt/Ge
      as the underlying implementation as this will only require swapping operands
      on MIPS and is consistent with x86/ARM instructions.
      
      BUG=v8:6020
      
      R=bbudge@chromium.org, bmeurer@chromium.org, bradnelson@chromium.org
      
      Review-Url: https://codereview.chromium.org/2874403002
      Cr-Commit-Position: refs/heads/master@{#45440}
      eeefc74a
  9. 15 May, 2017 1 commit
    • dusan.simicic's avatar
      MIPS[64]: Support for some SIMD operations (6) · b99a1ba0
      dusan.simicic authored
      Add support for I16x8Mul, I16x8MaxS, I16x8MinS, I16x8Eq, I16x8Ne,
      I16x8LtS, I16x8LeS, I16x8AddSaturateU, I16x8SubSaturateU, I16x8MaxU,
      I16x8MinU, I16x8LtU, I16x8LeU, I8x16Splat, I8x16ExtractLane,
      I8x16ReplaceLane, I8x16Neg, I8x16Shl, I8x16ShrS, S16x8Select,
      S8x16Select for mips32 and mips64 architectures.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2791213003
      Cr-Commit-Position: refs/heads/master@{#45312}
      b99a1ba0
  10. 04 May, 2017 1 commit
  11. 21 Apr, 2017 1 commit
    • bbudge's avatar
      [WASM SIMD] Remove opcodes that are slow on some platforms. · dddfcfd0
      bbudge authored
      These can be synthesized from existing operations and scheduled for
      better performance than if we have to generate blocks of instructions
      that take many cycles to complete.
      - Remove F32x4RecipRefine, F32x4RecipSqrtRefine. Clients are better off
        synthesizing these from splats, multiplies and adds.
      - Remove F32x4Div, F32x4Sqrt, F32x4MinNum, F32x4MaxNum. Clients are
        better off synthesizing these or using the reciprocal approximations,
        possibly with a refinement step.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2827143002
      Cr-Commit-Position: refs/heads/master@{#44784}
      dddfcfd0
  12. 12 Apr, 2017 1 commit
  13. 11 Apr, 2017 1 commit
  14. 04 Apr, 2017 1 commit
  15. 03 Apr, 2017 1 commit
  16. 15 Dec, 2016 1 commit
    • ivica.bogosavljevic's avatar
      MIPS[64]: Disable fusion multiple-accumulate instructions · ee7281f8
      ivica.bogosavljevic authored
      MIPS[64]R6 supports only fusion multiply-accumulate instructions, and using
      these causes failures of several tests that expect exact floating-point
      results. Therefore we disable fusion multiply-accumulate in both emitted and
      compiled code on R6.
      
      TEST=cctest/test-run-machops/RunFloat64MulAndFloat64Add1,mjsunit/es6/math-expm1.js
      mjsunit/es6/math-fround.js,mjsunit/compiler/multiply-add.js
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2569683002
      Cr-Commit-Position: refs/heads/master@{#41717}
      ee7281f8
  17. 22 Sep, 2016 1 commit
    • Ilija.Pavlovic's avatar
      MIPS: Port for (fused) multiply add/subtract. · 502b9aa7
      Ilija.Pavlovic authored
      Port for VisitFloat32Add, VisitFloat64Add, VisitFloat32Sub and
      VisitFloat64Sub in InstructionSelector.
      
      TEST=unittests/InstructionSelectorTest.Float32AddWithFloat32Mul,
           unittests/InstructionSelectorTest.Float64AddWithFloat64Mul,
           unittests/InstructionSelectorTest.Float32SubWithFloat32Mul,
           unittests/InstructionSelectorTest.Float64SubWithFloat64Mul
      BUG=
      
      Review-Url: https://codereview.chromium.org/2341303002
      Cr-Commit-Position: refs/heads/master@{#39616}
      502b9aa7
  18. 21 Sep, 2016 1 commit
  19. 22 Aug, 2016 1 commit
  20. 16 Aug, 2016 1 commit
  21. 08 Aug, 2016 1 commit
  22. 05 Aug, 2016 1 commit
  23. 22 Jul, 2016 2 commits
    • ivica.bogosavljevic's avatar
      Implement UnaligedLoad and UnaligedStore turbofan operators. · 580fdf3c
      ivica.bogosavljevic authored
      Implement UnalignedLoad and UnalignedStore optional
      turbofan operators and use them in WasmCompiler for unaligned
      memory access.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2122853002
      Cr-Commit-Position: refs/heads/master@{#37988}
      580fdf3c
    • bmeurer's avatar
      [turbofan] Change Float64Max/Float64Min to JavaScript semantics. · ba092fb0
      bmeurer authored
      So far we don't have a useful way to inline Math.max or Math.min in
      TurboFan optimized code. This adds new operators NumberMax and NumberMin
      and changes the Float64Max/Float64Min operators to have JavaScript
      semantics instead of the C++ semantics that it had previously.
      
      This also removes support for recognizing the tenary case in the
      CommonOperatorReducer, since that doesn't seem to have any positive
      impact (and actually doesn't show up in regular JavaScript, where
      people use Math.max/Math.min instead).
      
      Drive-by-fix: Also nuke the unused Float32Max/Float32Min operators.
      
      R=jarin@chromium.org
      
      Review-Url: https://codereview.chromium.org/2170343002
      Cr-Commit-Position: refs/heads/master@{#37971}
      ba092fb0
  24. 14 Jul, 2016 1 commit
  25. 20 Jun, 2016 1 commit
  26. 14 Jun, 2016 1 commit
  27. 10 Jun, 2016 1 commit
    • bmeurer's avatar
      [builtins] Introduce proper base::ieee754::log. · d0c7775d
      bmeurer authored
      This switches Math.log to use an fdlibm based version of log, imported
      as base::ieee754::log, and use that consistently everywhere, i.e. change
      the Float64Log TurboFan operators on Intel to use the C++ implementation
      as well (same for Crankshaft).
      
      R=yangguo@chromium.org
      BUG=v8:5065,v8:5086
      
      Review-Url: https://codereview.chromium.org/2053893003
      Cr-Commit-Position: refs/heads/master@{#36880}
      d0c7775d
  28. 03 Jun, 2016 1 commit
    • bmeurer's avatar
      [builtins] Migrate Math.log to TurboFan. · f2da19fe
      bmeurer authored
      Introduce a dedicated Float64Log machine operator, that is either
      implemented by a direct C call or by platform specific code, i.e.
      using the FPU on x64 and ia32.
      
      This operator is used to implement Math.log as a proper TurboFan
      builtin on top of the CodeStubAssembler.
      
      Also introduce a NumberLog simplified operator on top of Float64Log
      and use that for the fast inline path of Math.log inside TurboFan
      optimized code.
      
      BUG=v8:5065
      
      Review-Url: https://codereview.chromium.org/2029413005
      Cr-Commit-Position: refs/heads/master@{#36703}
      f2da19fe
  29. 06 Apr, 2016 2 commits
  30. 05 Apr, 2016 1 commit
  31. 18 Feb, 2016 2 commits
  32. 27 Jan, 2016 1 commit
  33. 18 Dec, 2015 1 commit
  34. 07 Dec, 2015 1 commit
  35. 01 Dec, 2015 1 commit
  36. 26 Nov, 2015 1 commit
  37. 20 Nov, 2015 1 commit