1. 22 Jul, 2020 3 commits
  2. 17 Jul, 2020 1 commit
    • Clemens Backes's avatar
      [liftoff] Fix missing stack move · 42b4f15a
      Clemens Backes authored
      The {operator==} on {VarState} did not check the spill offset, so when
      merging stack states, we forgot to move stack values if both source and
      destination were stack slots, but at different offsets.
      This CL fixes this by removing the {operator==}, because the semantics
      (and use) are not clear, and it's only used in one place anyway.
      The equality check was mostly redundant, so inlining it also makes the
      code smaller and faster.
      
      R=ahaas@chromium.org
      
      Bug: v8:10702
      Change-Id: I6c8b2cfd1002274175c9a17d305692e4631fd7dc
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2304574Reviewed-by: 's avatarAndreas Haas <ahaas@chromium.org>
      Commit-Queue: Clemens Backes <clemensb@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#68916}
      42b4f15a
  3. 10 Jul, 2020 1 commit
  4. 09 Jul, 2020 2 commits
  5. 26 Jun, 2020 1 commit
  6. 25 Jun, 2020 1 commit
  7. 10 Jun, 2020 1 commit
    • Clemens Backes's avatar
      [liftoff] Inline PopToRegister and outline SpillOneRegister · 52ddf949
      Clemens Backes authored
      {PopToRegister} will most likely find that the stack slot is already
      holding a register (89% of cases on epic). Thus put the fast path for
      this in the header, so it can be inlined.
      
      Also, {GetUnusedRegister} will mostly find an unused register (95% on
      epic). Hence, make sure that the code for spilling a register is not
      inlined.
      
      Drive-by: Avoid the call to {LoadToRegister} if we already checked
      before if the slot is holding a register.
      
      R=thibaudm@chromium.org
      
      Bug: v8:10576
      Change-Id: I13797fa5c12c5359f2578a4dbebb63aa50c00e60
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2237144
      Commit-Queue: Clemens Backes <clemensb@chromium.org>
      Reviewed-by: 's avatarThibaud Michaud <thibaudm@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#68280}
      52ddf949
  8. 06 Jun, 2020 1 commit
  9. 03 Jun, 2020 1 commit
  10. 02 Jun, 2020 2 commits
  11. 01 Jun, 2020 2 commits
  12. 29 May, 2020 1 commit
  13. 27 May, 2020 3 commits
  14. 20 May, 2020 1 commit
    • Ng Zhi An's avatar
      Reland "[wasm-simd][liftoff][x64][ia32] Implement load extend" · 6b228044
      Ng Zhi An authored
      This is a reland of dd19a400
      
      Original change's description:
      > [wasm-simd][liftoff][x64][ia32] Implement load extend
      > 
      > The operations are implemented:
      > 
      > - i16x8.load8x8_s
      > - i16x8.load8x8_u
      > - i32x4.load16x4_s
      > - i32x4.load16x4_u
      > - i64x2.load32x2_s
      > - i64x2.load32x2_u
      > 
      > on x64 and i32. The rest of the arch currently bail out, and will be
      > implemented in subsequent patches.
      > 
      > The liftoff-compiler.cc code looks very similar to the one for LoadMem,
      > the only difference is special handling of kSplat v.s. kExtend. kExtend
      > always loads 8 bytes, so the bounds check and tracing is different.
      > Compared to LoadMem there is less need for pinning, since the result is
      > always going to be in a SIMD/FP register, which is different from the
      > index/addr register.
      > 
      > The enum LoadTransformationKind was moved from
      > function-body-decoder-impl.h to function-body-decoder.h so that no
      > unncessary header file inclusions were needed to liftoff, and also it's
      > a better place for it to live.
      > 
      > Bug: v8:9909
      > Change-Id: I926bcc01c0c3c860223e8c08f91bc4ab3b75c399
      > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2203730
      > Commit-Queue: Zhi An Ng <zhin@chromium.org>
      > Reviewed-by: Clemens Backes <clemensb@chromium.org>
      > Cr-Commit-Position: refs/heads/master@{#67914}
      
      Bug: v8:9909
      Change-Id: Ic1d8dcc00d9c5af0d51100a947161eaa315b7659
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2209268Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
      Commit-Queue: Zhi An Ng <zhin@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#67930}
      6b228044
  15. 19 May, 2020 2 commits
    • Zhi An Ng's avatar
      Revert "[wasm-simd][liftoff][x64][ia32] Implement load extend" · 7bd682c9
      Zhi An Ng authored
      This reverts commit dd19a400.
      
      Reason for revert: https://ci.chromium.org/p/v8/builders/ci/V8%20Linux%20-%20debug/30448?
      
      Original change's description:
      > [wasm-simd][liftoff][x64][ia32] Implement load extend
      > 
      > The operations are implemented:
      > 
      > - i16x8.load8x8_s
      > - i16x8.load8x8_u
      > - i32x4.load16x4_s
      > - i32x4.load16x4_u
      > - i64x2.load32x2_s
      > - i64x2.load32x2_u
      > 
      > on x64 and i32. The rest of the arch currently bail out, and will be
      > implemented in subsequent patches.
      > 
      > The liftoff-compiler.cc code looks very similar to the one for LoadMem,
      > the only difference is special handling of kSplat v.s. kExtend. kExtend
      > always loads 8 bytes, so the bounds check and tracing is different.
      > Compared to LoadMem there is less need for pinning, since the result is
      > always going to be in a SIMD/FP register, which is different from the
      > index/addr register.
      > 
      > The enum LoadTransformationKind was moved from
      > function-body-decoder-impl.h to function-body-decoder.h so that no
      > unncessary header file inclusions were needed to liftoff, and also it's
      > a better place for it to live.
      > 
      > Bug: v8:9909
      > Change-Id: I926bcc01c0c3c860223e8c08f91bc4ab3b75c399
      > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2203730
      > Commit-Queue: Zhi An Ng <zhin@chromium.org>
      > Reviewed-by: Clemens Backes <clemensb@chromium.org>
      > Cr-Commit-Position: refs/heads/master@{#67914}
      
      TBR=clemensb@chromium.org,zhin@chromium.org
      
      Change-Id: I2af6dfe6cd163d0dbc9f3a5ad4bfc5e622e76b63
      No-Presubmit: true
      No-Tree-Checks: true
      No-Try: true
      Bug: v8:9909
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2207665Reviewed-by: 's avatarZhi An Ng <zhin@chromium.org>
      Commit-Queue: Zhi An Ng <zhin@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#67915}
      7bd682c9
    • Ng Zhi An's avatar
      [wasm-simd][liftoff][x64][ia32] Implement load extend · dd19a400
      Ng Zhi An authored
      The operations are implemented:
      
      - i16x8.load8x8_s
      - i16x8.load8x8_u
      - i32x4.load16x4_s
      - i32x4.load16x4_u
      - i64x2.load32x2_s
      - i64x2.load32x2_u
      
      on x64 and i32. The rest of the arch currently bail out, and will be
      implemented in subsequent patches.
      
      The liftoff-compiler.cc code looks very similar to the one for LoadMem,
      the only difference is special handling of kSplat v.s. kExtend. kExtend
      always loads 8 bytes, so the bounds check and tracing is different.
      Compared to LoadMem there is less need for pinning, since the result is
      always going to be in a SIMD/FP register, which is different from the
      index/addr register.
      
      The enum LoadTransformationKind was moved from
      function-body-decoder-impl.h to function-body-decoder.h so that no
      unncessary header file inclusions were needed to liftoff, and also it's
      a better place for it to live.
      
      Bug: v8:9909
      Change-Id: I926bcc01c0c3c860223e8c08f91bc4ab3b75c399
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2203730
      Commit-Queue: Zhi An Ng <zhin@chromium.org>
      Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#67914}
      dd19a400
  16. 15 May, 2020 4 commits
  17. 14 May, 2020 1 commit
  18. 13 May, 2020 2 commits
  19. 12 May, 2020 1 commit
  20. 06 May, 2020 1 commit
    • Andreas Haas's avatar
      [wasm][liftoff][arm] Implement CompareExchange · 90fa771d
      Andreas Haas authored
      This CL implements all variants of CompareExchange on arm.
      
      Implementing 64-bit CompareExchange on arm requires a lot of registers,
      with the additional constraint that the low-word register of new_value
      and result have to have an even register code, and that the corresponding
      high-word registers have a register code that is by one higher than the
      register code of the low-word register.
      
      This register allocation is achieved by assigning fixed registers to
      all values.
      
      R=clemensb@chromium.org, v8-arm-ports@googlegroups.com
      
      Bug: v8:10108
      Change-Id: I2edfde15e80db0d45621a461793018d88e997431
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2172791
      Commit-Queue: Andreas Haas <ahaas@chromium.org>
      Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#67592}
      90fa771d
  21. 29 Apr, 2020 3 commits
    • Ng Zhi An's avatar
      [wasm-simd][liftoff] Implement bitselect · 6bbcdc3d
      Ng Zhi An authored
      Tweak the register allocation logic in liftoff-compiler.cc. If we reuse
      src1 or src2 for dst, it complicates the logic in the codegen
      significantly. We will need to check which operand dst is equals to,
      back it up, then make sure the mask ends up in dst (since thats how vbsl
      and bsl works, the first operand holds the mask and is overwritten). By
      tweaking the allocation logic, no code gen is required for the other
      backends.
      
      Bug: v8:9909
      Change-Id: I17843322508b18247c91e5959cf1b996b7f6a61d
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2171468
      Commit-Queue: Zhi An Ng <zhin@chromium.org>
      Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#67481}
      6bbcdc3d
    • Andreas Haas's avatar
      [wasm][liftoff] Order registers in a register pair · f11a938a
      Andreas Haas authored
      With this CL the registers in a register pair get ordered such that the
      low word register always has a lower register code than the high word
      register. This should allow easier reasoning about the register
      allocation, and prevent some register allocation bugs.
      
      Background: for many operations in Liftoff, input registers are reused
      as output registers. With register pairs, input register pairs are
      reused as output register pairs. Additional reasoning, and sometimes
      even additional code is needed when the registers of the output register
      pair are swapped, i.e. when the high word register of the input becomes
      the low word register of the output. With this CL the additional
      reasoning is not necessary anymore, as the high word and low word
      registers would get swapped during register allocation.
      
      Additionally this CL fixes the logic of the last_spilled_regs list. This
      list stored the last spilled registers, but recorded only one of the two
      registers of a register pair. With this CL, both registers get recorded.
      
      This CL does not have a regression test. The regression test was more
      than 9000 lines long, and quite slow. I was not able to minimize it
      substantially. The test would be fragile by nature, as it has to create
      a special register configuration or otherwise does not test anything
      meaningful. All in all I think it's better not to add the test.
      
      R=clemensb@chromium.org
      
      Bug: chromium:1074586
      Change-Id: I4b2475b0c6537c7ce2e51fee281388cdd85f2953
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2168875Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
      Commit-Queue: Andreas Haas <ahaas@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#67473}
      f11a938a
    • jing.bao's avatar
      [wasm-simd][liftoff] Implement gt on x64 and ia32 · 22242cb1
      jing.bao authored
      Bug: v8:9909
      Change-Id: Ic75c75fa3693a59bf059cf852172900ad95a1941
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2169026
      Commit-Queue: Jing Bao <jing.bao@intel.com>
      Reviewed-by: 's avatarZhi An Ng <zhin@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#67461}
      22242cb1
  22. 28 Apr, 2020 1 commit
  23. 27 Apr, 2020 1 commit
  24. 23 Apr, 2020 1 commit
  25. 22 Apr, 2020 1 commit
  26. 21 Apr, 2020 1 commit