1. 11 Dec, 2017 1 commit
  2. 02 Dec, 2017 1 commit
    • Mathias Bynens's avatar
      Normalize casing of hexadecimal digits · 822be9b2
      Mathias Bynens authored
      This patch normalizes the casing of hexadecimal digits in escape
      sequences of the form `\xNN` and integer literals of the form
      `0xNNNN`.
      
      Previously, the V8 code base used an inconsistent mixture of uppercase
      and lowercase.
      
      Google’s C++ style guide uses uppercase in its examples:
      https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters
      
      Moreover, uppercase letters more clearly stand out from the lowercase
      `x` (or `u`) characters at the start, as well as lowercase letters
      elsewhere in strings.
      
      BUG=v8:7109
      TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org
      NOPRESUBMIT=true
      
      Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng
      Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6
      Reviewed-on: https://chromium-review.googlesource.com/804294
      Commit-Queue: Mathias Bynens <mathias@chromium.org>
      Reviewed-by: 's avatarJakob Kummerow <jkummerow@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#49810}
      822be9b2
  3. 13 Oct, 2017 1 commit
  4. 29 Sep, 2017 1 commit
  5. 13 Sep, 2017 1 commit
  6. 01 Sep, 2017 1 commit
  7. 11 Aug, 2017 1 commit
  8. 28 Jul, 2017 1 commit
    • sreten.kovacevic's avatar
      MIPS[64]: Port `[arm] Introduce UseScratchRegisterScope` · 3eb4de34
      sreten.kovacevic authored
      Add UseScratchRegisterScope for MIPS and use it instead of using at register directly.
      
      Original commit message:
      `Introduce a stripped down version of UseScratchRegisterScope for ARM and use it
      inside the assembler and macro-assembler. At the exception of the Call
      instructions, we now use this scope instead of using the ip register
      directly. This is inspired from how the ARM64 backend works.
      
      In general, the benefit of doing this is we can catch cases where ip is being
      used both by the caller and by the assembler. But more specifically, TurboFan
      reserves r9 as an extra scratch register because ip can already be used by the
      assembler. With this utility, we can isolate the cases in the code generator
      which need an extra register and potentially fix them, allowing us to give r9
      back to the register allocator.
      
      This patch uncovered places in the assembler where we were using ip
      unconditionally when we could have re-used the destination register instead.`
      
      Bug: 
      Change-Id: I1a35c1661579882801605337abfc95f75b47f052
      Reviewed-on: https://chromium-review.googlesource.com/574923
      Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
      Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
      Cr-Commit-Position: refs/heads/master@{#46963}
      3eb4de34
  9. 31 May, 2017 1 commit
    • neis's avatar
      [compiler] Delay allocation of code-embedded heap numbers. · 659e8f7b
      neis authored
      Instead of allocating and embedding certain heap numbers into the code
      during code assembly, emit dummies but record the allocation requests.
      Later then, in Assembler::GetCode, allocate the heap numbers and patch
      the code by replacing the dummies with the actual objects. The
      RelocInfos for the embedded objects are already recorded correctly when
      emitting the dummies.
      
      R=jarin@chromium.org
      BUG=v8:6048
      
      Review-Url: https://codereview.chromium.org/2900683002
      Cr-Commit-Position: refs/heads/master@{#45635}
      659e8f7b
  10. 20 Apr, 2017 1 commit
  11. 07 Feb, 2017 1 commit
  12. 08 Dec, 2016 1 commit
    • Ilija.Pavlovic's avatar
      MIPS[64]: Fix `MIPS: Improve Float(32|64)(Max|Min)`. · e8f5adbe
      Ilija.Pavlovic authored
      Fix 7a6f294f.
      
      The first correction enables correct execution DoMathMinMax when two
      input registers are the same register.
      The second correction adds NOP instructions after branch instructions
      in tests macro_float_minmaxf(32|64).
      
      TEST=cctest/test-macro-assembler-mips[64]/macro_float_minmax_f32
           cctest/test-macro-assembler-mips[64]/macro_float_minmax_f64
           mjsunit/regress/math-min
      BUG=
      
      Review-Url: https://codereview.chromium.org/2556793003
      Cr-Commit-Position: refs/heads/master@{#41596}
      e8f5adbe
  13. 07 Dec, 2016 1 commit
  14. 06 Dec, 2016 1 commit
  15. 01 Dec, 2016 2 commits
  16. 20 Oct, 2016 1 commit
  17. 30 Sep, 2016 1 commit
    • akos.palfi's avatar
      MIPS: Fix Sltu macro instruction. · cb1084a8
      akos.palfi authored
      Fixes the case when the 'imm' is in range [8000,ffff], as the specification
      says the 'imm' is sign-extended before the comparsion, so the effective range
      is [max_unsigned-7fff,max_unsigned].
      
      TEST=mjsunit/generated-transition-stub@3b8ad45e
      BUG=
      
      Review-Url: https://codereview.chromium.org/2386673002
      Cr-Commit-Position: refs/heads/master@{#39922}
      cb1084a8
  18. 16 Aug, 2016 1 commit
  19. 10 Aug, 2016 1 commit
    • marija.antic's avatar
      MIPS: Implement Bovc and Bnvc instruction macros. · 93809055
      marija.antic authored
      Implement Bovc and Bnvc instruction macros in macro assembler.
      
      The change 6f920d7d revealed an issue with AddBranchOvf for mips R6.
      All branching instructions other than BOVC and BNVC are handled by Branch macro, which assures
      correct handling of long and short branches. As a consequence, AddBranchOvf for R6 was working correctly
      only before trampoline was emitted, but the case of long branch was not handled at all. Implemented
      instruction macros enable proper handling of BOVC and BNVC in cases when long branching is needed.
      
      TEST=test/intl/general/case-mapping.js
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2225323002
      Cr-Commit-Position: refs/heads/master@{#38513}
      93809055
  20. 27 Jun, 2016 1 commit
  21. 28 Apr, 2016 1 commit
  22. 07 Apr, 2016 1 commit
  23. 25 Mar, 2016 1 commit
  24. 18 Mar, 2016 1 commit
  25. 10 Mar, 2016 1 commit
  26. 09 Mar, 2016 1 commit
  27. 03 Feb, 2016 1 commit
  28. 13 Jan, 2016 1 commit
  29. 12 Jan, 2016 1 commit
  30. 06 Jan, 2016 1 commit
    • ivica.bogosavljevic's avatar
      MIPS64: r6 compact branch optimization. · 2c63060f
      ivica.bogosavljevic authored
      Several ports to enable r6 compact branch optimizations on MIPS64
      
      Port 3573d3cb
      
      Original commit message:
      MIPS: r6 compact branch optimization.
      
      Port bddf8c9e
      
      Original commit message:
      MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort()
      
      Port 6993cd0d
      
      Original commit message:
      MIPS: Fix 'MIPS:r6 compact branch optimization.'
      
      Jic and jialc compact branch ops are fixed as they does
      not have 'forbidden slot' restriction. Also COP1 branches
      (CTI instructions) added to IsForbiddenAfterBranchInstr().
      
      Port bb332195
      
      Original commit message:
      MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort()
      
      Port c91bcf71
      
      Original commit message:
      MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort()
      for r6.
      
      BUG=
      
      Review URL: https://codereview.chromium.org/1534183002
      
      Cr-Commit-Position: refs/heads/master@{#33136}
      2c63060f
  31. 05 Jan, 2016 1 commit
  32. 09 Dec, 2015 1 commit
  33. 25 Nov, 2015 1 commit
  34. 23 Nov, 2015 2 commits
  35. 16 Nov, 2015 1 commit
  36. 13 Jul, 2015 1 commit
  37. 09 Jul, 2014 1 commit
  38. 30 Jun, 2014 1 commit