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Commit fce4faaf authored by Ivo Markovic's avatar Ivo Markovic Committed by Commit Bot
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MIPS[64]: Fix register validation on R6 

Bug: 
Change-Id: I62414a59246af359634b1309b03216c0a5c8764b
Reviewed-on: https://chromium-review.googlesource.com/663728Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#48090}
parent b2ef3777
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Showing with 20 additions and 20 deletions
src/mips/macro-assembler-mips.cc
View file @ fce4faaf
......@@ -2741,7 +2741,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
bc(offset);
break;
case eq:
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
// Pre R6 beq is used here to make the code patchable. Otherwise bc
// should be used which has no condition field so is not patchable.
if (!CalculateOffset(L, offset, OffsetSize::kOffset16, scratch, rt))
......@@ -2759,7 +2759,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
}
break;
case ne:
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
// Pre R6 bne is used here to make the code patchable. Otherwise we
// should not generate any instruction.
if (!CalculateOffset(L, offset, OffsetSize::kOffset16, scratch, rt))
......@@ -2780,7 +2780,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
// Signed comparison.
case greater:
// rs > rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
break; // No code needs to be emitted.
} else if (rs == zero_reg) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset16, scratch, rt))
......@@ -2798,7 +2798,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case greater_equal:
// rs >= rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset26)) return false;
bc(offset);
} else if (rs == zero_reg) {
......@@ -2817,7 +2817,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case less:
// rs < rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
break; // No code needs to be emitted.
} else if (rs == zero_reg) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset16, scratch, rt))
......@@ -2835,7 +2835,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case less_equal:
// rs <= rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset26)) return false;
bc(offset);
} else if (rs == zero_reg) {
......@@ -2856,7 +2856,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
// Unsigned comparison.
case Ugreater:
// rs > rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
break; // No code needs to be emitted.
} else if (rs == zero_reg) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset21, scratch, rt))
......@@ -2874,7 +2874,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case Ugreater_equal:
// rs >= rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset26)) return false;
bc(offset);
} else if (rs == zero_reg) {
......@@ -2893,7 +2893,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case Uless:
// rs < rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
break; // No code needs to be emitted.
} else if (rs == zero_reg) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset21, scratch, rt))
......@@ -2910,7 +2910,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case Uless_equal:
// rs <= rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset26)) return false;
bc(offset);
} else if (rs == zero_reg) {
......
src/mips64/macro-assembler-mips64.cc
View file @ fce4faaf
......@@ -3206,7 +3206,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
bc(offset);
break;
case eq:
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
// Pre R6 beq is used here to make the code patchable. Otherwise bc
// should be used which has no condition field so is not patchable.
if (!CalculateOffset(L, offset, OffsetSize::kOffset16, scratch, rt))
......@@ -3224,7 +3224,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
}
break;
case ne:
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
// Pre R6 bne is used here to make the code patchable. Otherwise we
// should not generate any instruction.
if (!CalculateOffset(L, offset, OffsetSize::kOffset16, scratch, rt))
......@@ -3245,7 +3245,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
// Signed comparison.
case greater:
// rs > rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
break; // No code needs to be emitted.
} else if (rs == zero_reg) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset16, scratch, rt))
......@@ -3263,7 +3263,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case greater_equal:
// rs >= rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset26)) return false;
bc(offset);
} else if (rs == zero_reg) {
......@@ -3282,7 +3282,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case less:
// rs < rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
break; // No code needs to be emitted.
} else if (rs == zero_reg) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset16, scratch, rt))
......@@ -3300,7 +3300,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case less_equal:
// rs <= rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset26)) return false;
bc(offset);
} else if (rs == zero_reg) {
......@@ -3321,7 +3321,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
// Unsigned comparison.
case Ugreater:
// rs > rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
break; // No code needs to be emitted.
} else if (rs == zero_reg) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset21, scratch, rt))
......@@ -3339,7 +3339,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case Ugreater_equal:
// rs >= rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset26)) return false;
bc(offset);
} else if (rs == zero_reg) {
......@@ -3358,7 +3358,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case Uless:
// rs < rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
break; // No code needs to be emitted.
} else if (rs == zero_reg) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset21, scratch, rt))
......@@ -3375,7 +3375,7 @@ bool TurboAssembler::BranchShortHelperR6(int32_t offset, Label* L,
break;
case Uless_equal:
// rs <= rt
if (rs.code() == rt.rm().code()) {
if (rt.is_reg() && rs.code() == rt.rm().code()) {
if (!CalculateOffset(L, offset, OffsetSize::kOffset26)) return false;
bc(offset);
} else if (rs == zero_reg) {
......
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