Commit fccbf1b8 authored by Milad Fa's avatar Milad Fa Committed by Commit Bot

PPC: Adding more vector opcodes to the dissembler

Change-Id: I4e70f176fa08c9a6b6f40683248d4c32c8e16f59
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2598588Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71865}
parent 6e9f33f9
...@@ -526,7 +526,9 @@ using Instr = uint32_t; ...@@ -526,7 +526,9 @@ using Instr = uint32_t;
/* VSX Vector Test for software Square Root Double-Precision */ \ /* VSX Vector Test for software Square Root Double-Precision */ \
V(xvtsqrtdp, XVTSQRTDP, 0xF00003A8) \ V(xvtsqrtdp, XVTSQRTDP, 0xF00003A8) \
/* VSX Vector Test for software Square Root Single-Precision */ \ /* VSX Vector Test for software Square Root Single-Precision */ \
V(xvtsqrtsp, XVTSQRTSP, 0xF00002A8) V(xvtsqrtsp, XVTSQRTSP, 0xF00002A8) \
/* Vector Splat Immediate Byte */ \
V(xxspltib, XXSPLTIB, 0xF00002D0)
#define PPC_XX2_OPCODE_LIST(V) \ #define PPC_XX2_OPCODE_LIST(V) \
PPC_XX2_OPCODE_A_FORM_LIST(V) \ PPC_XX2_OPCODE_A_FORM_LIST(V) \
...@@ -2008,9 +2010,7 @@ using Instr = uint32_t; ...@@ -2008,9 +2010,7 @@ using Instr = uint32_t;
/* Store VSR Vector Doubleword*2 Indexed */ \ /* Store VSR Vector Doubleword*2 Indexed */ \
V(stxvd, STXVD, 0x7C000798) \ V(stxvd, STXVD, 0x7C000798) \
/* Store VSR Vector Word*4 Indexed */ \ /* Store VSR Vector Word*4 Indexed */ \
V(stxvw, STXVW, 0x7C000718) \ V(stxvw, STXVW, 0x7C000718)
/* Vector Splat Immediate Byte */ \
V(xxspltib, XXSPLTIB, 0xF00002D1)
#define PPC_B_OPCODE_LIST(V) \ #define PPC_B_OPCODE_LIST(V) \
/* Branch Conditional */ \ /* Branch Conditional */ \
......
...@@ -255,6 +255,11 @@ int Decoder::FormatOption(Instruction* instr, const char* format) { ...@@ -255,6 +255,11 @@ int Decoder::FormatOption(Instruction* instr, const char* format) {
out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
return 5; return 5;
} }
case 'I': { // IMM8
int8_t value = instr->Bits(18, 11);
out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
return 4;
}
case 'u': { // uint16 case 'u': { // uint16
int32_t value = instr->Bits(15, 0); int32_t value = instr->Bits(15, 0);
out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
...@@ -400,104 +405,29 @@ void Decoder::UnknownFormat(Instruction* instr, const char* name) { ...@@ -400,104 +405,29 @@ void Decoder::UnknownFormat(Instruction* instr, const char* name) {
void Decoder::DecodeExt0(Instruction* instr) { void Decoder::DecodeExt0(Instruction* instr) {
// Some encodings are 5-0 bits, handle those first // Some encodings are 5-0 bits, handle those first
switch (EXT0 | (instr->BitField(5, 0))) { switch (EXT0 | (instr->BitField(5, 0))) {
case VPERM: { #define DECODE_VA_A_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
Format(instr, "vperm 'Vt, 'Va, 'Vb, 'Vc"); case opcode_name: { \
return; Format(instr, #name " 'Vt, 'Va, 'Vb, 'Vc"); \
} return; \
case VMLADDUHM: { }
Format(instr, "vmladduhm 'Vt, 'Va, 'Vb, 'Vc"); PPC_VA_OPCODE_A_FORM_LIST(DECODE_VA_A_FORM__INSTRUCTIONS)
return; #undef DECODE_VA_A_FORM__INSTRUCTIONS
}
} }
switch (EXT0 | (instr->BitField(10, 0))) { switch (EXT0 | (instr->BitField(10, 0))) {
case VSPLTB: { #define DECODE_VX_A_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
Format(instr, "vspltb 'Vt, 'Vb, 'UIM"); case opcode_name: { \
break; Format(instr, #name " 'Vt, 'Vb, 'UIM"); \
} return; \
case VSPLTW: { }
Format(instr, "vspltw 'Vt, 'Vb, 'UIM"); PPC_VX_OPCODE_A_FORM_LIST(DECODE_VX_A_FORM__INSTRUCTIONS)
break; #undef DECODE_VX_A_FORM__INSTRUCTIONS
} #define DECODE_VX_B_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
case VSPLTH: { case opcode_name: { \
Format(instr, "vsplth 'Vt, 'Vb, 'UIM"); Format(instr, #name " 'Vt, 'Va, 'Vb"); \
break; return; \
} }
case VSRO: { PPC_VX_OPCODE_B_FORM_LIST(DECODE_VX_B_FORM__INSTRUCTIONS)
Format(instr, "vsro 'Vt, 'Va, 'Vb"); #undef DECODE_VX_B_FORM__INSTRUCTIONS
break;
}
case VOR: {
Format(instr, "vor 'Vt, 'Va, 'Vb");
break;
}
case VXOR: {
Format(instr, "vxor 'Vt, 'Va, 'Vb");
break;
}
case VNOR: {
Format(instr, "vnor 'Vt, 'Va, 'Vb");
break;
}
case VSLO: {
Format(instr, "vslo 'Vt, 'Va, 'Vb");
break;
}
case VADDUDM: {
Format(instr, "vaddudm 'Vt, 'Va, 'Vb");
break;
}
case VADDUWM: {
Format(instr, "vadduwm 'Vt, 'Va, 'Vb");
break;
}
case VADDUHM: {
Format(instr, "vadduhm 'Vt, 'Va, 'Vb");
break;
}
case VADDUBM: {
Format(instr, "vaddubm 'Vt, 'Va, 'Vb");
break;
}
case VADDFP: {
Format(instr, "vaddfp 'Vt, 'Va, 'Vb");
break;
}
case VSUBFP: {
Format(instr, "vsubfp 'Vt, 'Va, 'Vb");
break;
}
case VSUBUDM: {
Format(instr, "vsubudm 'Vt, 'Va, 'Vb");
break;
}
case VSUBUWM: {
Format(instr, "vsubuwm 'Vt, 'Va, 'Vb");
break;
}
case VSUBUHM: {
Format(instr, "vsubuhm 'Vt, 'Va, 'Vb");
break;
}
case VSUBUBM: {
Format(instr, "vsububm 'Vt, 'Va, 'Vb");
break;
}
case VMULUWM: {
Format(instr, "vmuluwm 'Vt, 'Va, 'Vb");
break;
}
case VPKUHUM: {
Format(instr, "vpkuhum 'Vt, 'Va, 'Vb");
break;
}
case VMULEUB: {
Format(instr, "vmuleub 'Vt, 'Va, 'Vb");
break;
}
case VMULOUB: {
Format(instr, "vmuloub 'Vt, 'Va, 'Vb");
break;
}
} }
} }
...@@ -686,10 +616,42 @@ void Decoder::DecodeExt2(Instruction* instr) { ...@@ -686,10 +616,42 @@ void Decoder::DecodeExt2(Instruction* instr) {
Format(instr, "lxvd 'Xt, 'ra, 'rb"); Format(instr, "lxvd 'Xt, 'ra, 'rb");
return; return;
} }
case LXSDX: {
Format(instr, "lxsdx 'Xt, 'ra, 'rb");
return;
}
case LXSIBZX: {
Format(instr, "lxsibzx 'Xt, 'ra, 'rb");
return;
}
case LXSIHZX: {
Format(instr, "lxsihzx 'Xt, 'ra, 'rb");
return;
}
case LXSIWZX: {
Format(instr, "lxsiwzx 'Xt, 'ra, 'rb");
return;
}
case STXVD: { case STXVD: {
Format(instr, "stxvd 'Xs, 'ra, 'rb"); Format(instr, "stxvd 'Xs, 'ra, 'rb");
return; return;
} }
case STXSDX: {
Format(instr, "stxsdx 'Xs, 'ra, 'rb");
return;
}
case STXSIBX: {
Format(instr, "stxsibx 'Xs, 'ra, 'rb");
return;
}
case STXSIHX: {
Format(instr, "stxsihx 'Xs, 'ra, 'rb");
return;
}
case STXSIWX: {
Format(instr, "stxsiwx 'Xs, 'ra, 'rb");
return;
}
case SRWX: { case SRWX: {
Format(instr, "srw'. 'ra, 'rs, 'rb"); Format(instr, "srw'. 'ra, 'rs, 'rb");
return; return;
...@@ -1083,6 +1045,10 @@ void Decoder::DecodeExt2(Instruction* instr) { ...@@ -1083,6 +1045,10 @@ void Decoder::DecodeExt2(Instruction* instr) {
Format(instr, "mtfprwz 'Dt, 'ra"); Format(instr, "mtfprwz 'Dt, 'ra");
return; return;
} }
case MTVSRDD: {
Format(instr, "mtvsrwz 'Xt, 'ra");
return;
}
#endif #endif
} }
...@@ -1281,24 +1247,30 @@ void Decoder::DecodeExt5(Instruction* instr) { ...@@ -1281,24 +1247,30 @@ void Decoder::DecodeExt5(Instruction* instr) {
} }
void Decoder::DecodeExt6(Instruction* instr) { void Decoder::DecodeExt6(Instruction* instr) {
switch (EXT6 | (instr->BitField(10, 1))) {
case XXSPLTIB: {
Format(instr, "xxspltib 'Xt, 'IMM8");
return;
}
}
switch (EXT6 | (instr->BitField(10, 3))) { switch (EXT6 | (instr->BitField(10, 3))) {
#define DECODE_XX3_INSTRUCTIONS(name, opcode_name, opcode_value) \ #define DECODE_XX3_INSTRUCTIONS(name, opcode_name, opcode_value) \
case opcode_name: { \ case opcode_name: { \
Format(instr, #name " 'Dt, 'Da, 'Db"); \ Format(instr, #name " 'Xt, 'Xa, 'Xb"); \
return; \ return; \
} }
PPC_XX3_OPCODE_LIST(DECODE_XX3_INSTRUCTIONS) PPC_XX3_OPCODE_LIST(DECODE_XX3_INSTRUCTIONS)
#undef DECODE_XX3_INSTRUCTIONS #undef DECODE_XX3_INSTRUCTIONS
} }
switch (EXT6 | (instr->BitField(10, 2))) { switch (EXT6 | (instr->BitField(10, 2))) {
#define DECODE_XX2_INSTRUCTIONS(name, opcode_name, opcode_value) \ #define DECODE_XX2_A_INSTRUCTIONS(name, opcode_name, opcode_value) \
case opcode_name: { \ case opcode_name: { \
Format(instr, #name " 'Dt, 'Db"); \ Format(instr, #name " 'Xt, 'Xb"); \
return; \ return; \
} }
PPC_XX2_OPCODE_LIST(DECODE_XX2_INSTRUCTIONS) PPC_XX2_OPCODE_A_FORM_LIST(DECODE_XX2_A_INSTRUCTIONS)
} }
#undef DECODE_XX2_INSTRUCTIONS #undef DECODE_XX2_A_INSTRUCTIONS
Unknown(instr); // not used by V8 Unknown(instr); // not used by V8
} }
......
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