Commit fb6d80fa authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

PPC [liftoff]: Implement a number of Simd ops

- LoadCallerFrameSlot
- StoreCallerFrameSlot
- LoadReturnStackSlot
- MoveStackValue
- Spill
- Fill

Change-Id: I5fee06a60b36ec145b4d35d59ede35bb849e57b8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3851544Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#82751}
parent c75d6b7a
...@@ -833,7 +833,7 @@ void LiftoffAssembler::LoadCallerFrameSlot(LiftoffRegister dst, ...@@ -833,7 +833,7 @@ void LiftoffAssembler::LoadCallerFrameSlot(LiftoffRegister dst,
break; break;
} }
case kS128: { case kS128: {
bailout(kSimd, "simd load"); LoadSimd128(dst.fp().toSimd(), MemOperand(fp, offset), r0);
break; break;
} }
default: default:
...@@ -871,7 +871,7 @@ void LiftoffAssembler::StoreCallerFrameSlot(LiftoffRegister src, ...@@ -871,7 +871,7 @@ void LiftoffAssembler::StoreCallerFrameSlot(LiftoffRegister src,
break; break;
} }
case kS128: { case kS128: {
bailout(kSimd, "simd load"); StoreSimd128(src.fp().toSimd(), MemOperand(fp, offset), r0);
break; break;
} }
default: default:
...@@ -907,7 +907,7 @@ void LiftoffAssembler::LoadReturnStackSlot(LiftoffRegister dst, int offset, ...@@ -907,7 +907,7 @@ void LiftoffAssembler::LoadReturnStackSlot(LiftoffRegister dst, int offset,
break; break;
} }
case kS128: { case kS128: {
bailout(kSimd, "simd load"); LoadSimd128(dst.fp().toSimd(), MemOperand(sp, offset), r0);
break; break;
} }
default: default:
...@@ -940,7 +940,8 @@ void LiftoffAssembler::MoveStackValue(uint32_t dst_offset, uint32_t src_offset, ...@@ -940,7 +940,8 @@ void LiftoffAssembler::MoveStackValue(uint32_t dst_offset, uint32_t src_offset,
StoreU64(ip, liftoff::GetStackSlot(dst_offset), r0); StoreU64(ip, liftoff::GetStackSlot(dst_offset), r0);
break; break;
case kS128: case kS128:
bailout(kSimd, "simd op"); LoadSimd128(kScratchSimd128Reg, liftoff::GetStackSlot(src_offset), r0);
StoreSimd128(kScratchSimd128Reg, liftoff::GetStackSlot(dst_offset), r0);
break; break;
default: default:
UNREACHABLE(); UNREACHABLE();
...@@ -956,7 +957,8 @@ void LiftoffAssembler::Move(DoubleRegister dst, DoubleRegister src, ...@@ -956,7 +957,8 @@ void LiftoffAssembler::Move(DoubleRegister dst, DoubleRegister src,
if (kind == kF32 || kind == kF64) { if (kind == kF32 || kind == kF64) {
fmr(dst, src); fmr(dst, src);
} else { } else {
bailout(kSimd, "simd op"); DCHECK_EQ(kS128, kind);
vor(dst.toSimd(), src.toSimd(), src.toSimd());
} }
} }
...@@ -981,7 +983,7 @@ void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { ...@@ -981,7 +983,7 @@ void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) {
StoreF64(reg.fp(), liftoff::GetStackSlot(offset), r0); StoreF64(reg.fp(), liftoff::GetStackSlot(offset), r0);
break; break;
case kS128: { case kS128: {
bailout(kSimd, "simd op"); StoreSimd128(reg.fp().toSimd(), liftoff::GetStackSlot(offset), r0);
break; break;
} }
default: default:
...@@ -1029,7 +1031,7 @@ void LiftoffAssembler::Fill(LiftoffRegister reg, int offset, ValueKind kind) { ...@@ -1029,7 +1031,7 @@ void LiftoffAssembler::Fill(LiftoffRegister reg, int offset, ValueKind kind) {
LoadF64(reg.fp(), liftoff::GetStackSlot(offset), r0); LoadF64(reg.fp(), liftoff::GetStackSlot(offset), r0);
break; break;
case kS128: { case kS128: {
bailout(kSimd, "simd op"); LoadSimd128(reg.fp().toSimd(), liftoff::GetStackSlot(offset), r0);
break; break;
} }
default: default:
......
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