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Commit f91231f1 authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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PPC: [wasm-simd] Implement simd saturate binary operations 

Change-Id: I7989934f7f8a1332045a6ed708b02fbc3424c829
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2310911Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68993}
parent a269ce20
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Showing with 81 additions and 49 deletions
src/codegen/ppc/constants-ppc.h
View file @ f91231f1
......@@ -2322,7 +2322,23 @@ using Instr = uint32_t;
/* Vector Pack Signed Halfword Signed Saturate */ \
V(vpkshss, VPKSHSS, 0x1000018E) \
/* Vector Pack Signed Halfword Unsigned Saturate */ \
V(vpkshus, VPKSHUS, 0x1000010E)
V(vpkshus, VPKSHUS, 0x1000010E) \
/* Vector Add Signed Halfword Saturate */ \
V(vaddshs, VADDSHS, 0x10000340) \
/* Vector Subtract Signed Halfword Saturate */ \
V(vsubshs, VSUBSHS, 0x10000740) \
/* Vector Add Unsigned Halfword Saturate */ \
V(vadduhs, VADDUHS, 0x10000240) \
/* Vector Subtract Unsigned Halfword Saturate */ \
V(vsubuhs, VSUBUHS, 0x10000640) \
/* Vector Add Signed Byte Saturate */ \
V(vaddsbs, VADDSBS, 0x10000300) \
/* Vector Subtract Signed Byte Saturate */ \
V(vsubsbs, VSUBSBS, 0x10000700) \
/* Vector Add Unsigned Byte Saturate */ \
V(vaddubs, VADDUBS, 0x10000200) \
/* Vector Subtract Unsigned Byte Saturate */ \
V(vsububs, VSUBUBS, 0x10000600)
#define PPC_VX_OPCODE_C_FORM_LIST(V) \
/* Vector Unpack Low Signed Halfword */ \
......@@ -2347,16 +2363,8 @@ using Instr = uint32_t;
V(vaddcuq, VADDCUQ, 0x10000140) \
/* Vector Add and Write Carry-Out Unsigned Word */ \
V(vaddcuw, VADDCUW, 0x10000180) \
/* Vector Add Signed Byte Saturate */ \
V(vaddsbs, VADDSBS, 0x10000300) \
/* Vector Add Signed Halfword Saturate */ \
V(vaddshs, VADDSHS, 0x10000340) \
/* Vector Add Signed Word Saturate */ \
V(vaddsws, VADDSWS, 0x10000380) \
/* Vector Add Unsigned Byte Saturate */ \
V(vaddubs, VADDUBS, 0x10000200) \
/* Vector Add Unsigned Halfword Saturate */ \
V(vadduhs, VADDUHS, 0x10000240) \
/* Vector Add Unsigned Quadword Modulo */ \
V(vadduqm, VADDUQM, 0x10000100) \
/* Vector Add Unsigned Word Saturate */ \
......@@ -2505,16 +2513,8 @@ using Instr = uint32_t;
V(vsubcuq, VSUBCUQ, 0x10000540) \
/* Vector Subtract and Write Carry-Out Unsigned Word */ \
V(vsubcuw, VSUBCUW, 0x10000580) \
/* Vector Subtract Signed Byte Saturate */ \
V(vsubsbs, VSUBSBS, 0x10000700) \
/* Vector Subtract Signed Halfword Saturate */ \
V(vsubshs, VSUBSHS, 0x10000740) \
/* Vector Subtract Signed Word Saturate */ \
V(vsubsws, VSUBSWS, 0x10000780) \
/* Vector Subtract Unsigned Byte Saturate */ \
V(vsububs, VSUBUBS, 0x10000600) \
/* Vector Subtract Unsigned Halfword Saturate */ \
V(vsubuhs, VSUBUHS, 0x10000640) \
/* Vector Subtract Unsigned Quadword Modulo */ \
V(vsubuqm, VSUBUQM, 0x10000500) \
/* Vector Subtract Unsigned Word Saturate */ \
......
src/compiler/backend/ppc/code-generator-ppc.cc
View file @ f91231f1
......@@ -3193,6 +3193,46 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vperm(dst, src0, src1, kScratchDoubleReg);
break;
}
case kPPC_I16x8AddSaturateS: {
__ vaddshs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8SubSaturateS: {
__ vsubshs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8AddSaturateU: {
__ vadduhs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8SubSaturateU: {
__ vsubuhs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16AddSaturateS: {
__ vaddsbs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16SubSaturateS: {
__ vsubsbs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16AddSaturateU: {
__ vaddubs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16SubSaturateU: {
__ vsububs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_StoreCompressTagged: {
ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
break;
......
src/compiler/backend/ppc/instruction-codes-ppc.h
View file @ f91231f1
......@@ -298,6 +298,10 @@ namespace compiler {
V(PPC_I16x8SConvertI8x16High) \
V(PPC_I16x8UConvertI8x16Low) \
V(PPC_I16x8UConvertI8x16High) \
V(PPC_I16x8AddSaturateS) \
V(PPC_I16x8SubSaturateS) \
V(PPC_I16x8AddSaturateU) \
V(PPC_I16x8SubSaturateU) \
V(PPC_I8x16Splat) \
V(PPC_I8x16ExtractLaneU) \
V(PPC_I8x16ExtractLaneS) \
......@@ -322,6 +326,10 @@ namespace compiler {
V(PPC_I8x16Abs) \
V(PPC_I8x16SConvertI16x8) \
V(PPC_I8x16UConvertI16x8) \
V(PPC_I8x16AddSaturateS) \
V(PPC_I8x16SubSaturateS) \
V(PPC_I8x16AddSaturateU) \
V(PPC_I8x16SubSaturateU) \
V(PPC_S8x16Shuffle) \
V(PPC_V64x2AnyTrue) \
V(PPC_V32x4AnyTrue) \
......
src/compiler/backend/ppc/instruction-scheduler-ppc.cc
View file @ f91231f1
......@@ -221,6 +221,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I16x8SConvertI8x16High:
case kPPC_I16x8UConvertI8x16Low:
case kPPC_I16x8UConvertI8x16High:
case kPPC_I16x8AddSaturateS:
case kPPC_I16x8SubSaturateS:
case kPPC_I16x8AddSaturateU:
case kPPC_I16x8SubSaturateU:
case kPPC_I8x16Splat:
case kPPC_I8x16ExtractLaneU:
case kPPC_I8x16ExtractLaneS:
......@@ -245,6 +249,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I8x16Abs:
case kPPC_I8x16SConvertI16x8:
case kPPC_I8x16UConvertI16x8:
case kPPC_I8x16AddSaturateS:
case kPPC_I8x16SubSaturateS:
case kPPC_I8x16AddSaturateU:
case kPPC_I8x16SubSaturateU:
case kPPC_S8x16Shuffle:
case kPPC_V64x2AnyTrue:
case kPPC_V32x4AnyTrue:
......
src/compiler/backend/ppc/instruction-selector-ppc.cc
View file @ f91231f1
......@@ -2181,6 +2181,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8GeU) \
V(I16x8SConvertI32x4) \
V(I16x8UConvertI32x4) \
V(I16x8AddSaturateS) \
V(I16x8SubSaturateS) \
V(I16x8AddSaturateU) \
V(I16x8SubSaturateU) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16Mul) \
......@@ -2196,6 +2200,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16GeU) \
V(I8x16SConvertI16x8) \
V(I8x16UConvertI16x8) \
V(I8x16AddSaturateS) \
V(I8x16SubSaturateS) \
V(I8x16AddSaturateU) \
V(I8x16SubSaturateU) \
V(S128And) \
V(S128Or) \
V(S128Xor)
......@@ -2373,22 +2381,6 @@ void InstructionSelector::VisitS128Select(Node* node) {
void InstructionSelector::VisitS128Const(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) {
UNIMPLEMENTED();
}
......@@ -2397,22 +2389,6 @@ void InstructionSelector::VisitI8x16RoundingAverageU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16SubSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16AddSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16SubSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::EmitPrepareResults(
......
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