cpu-arm: Add noinline to cache flushing logic

This is an attempt to work around a potential toolchain bug.

Disassembly of FlushICache:

00000000 <_ZN2v88internal11CpuFeatures11FlushICacheEPvj>:
     0:·b5c0      ··push··{r6, r7, lr}
     2:·af01      ··add·r7, sp, #4
     4:·2702      ··movs··r7, #2
     6:·4401      ··add·r1, r0
     8:·f2c0 070f ··movt··r7, #15
     c:·2200      ··movs··r2, #0
     e:·df00      ··svc·0
    10:·bdc0      ··pop·{r6, r7, pc}

Bug: chromium:952759
Change-Id: I6a618607f58c394c364b2ebd9f11684871a8beee
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1579542
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Cr-Commit-Position: refs/heads/master@{#60966}

src/arm/cpu-arm.cc

@@ -19,7 +19,10 @@
 namespace v8 {
 namespace internal {
 
-void CpuFeatures::FlushICache(void* start, size_t size) {
+// The inlining of this seems to trigger an LTO bug that clobbers a register on
+// arm, see https://crbug.com/952759#c6.
+__attribute__((noinline)) void CpuFeatures::FlushICache(void* start,
+                                                        size_t size) {
 #if !defined(USE_SIMULATOR)
 #if V8_OS_QNX
   msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);