[arm64][Liftoff] implement conditional set instructions

Bug: v8:6600
Change-Id: If52fd4600c178354cb0631d062be71d19cc10a89
Reviewed-on: https://chromium-review.googlesource.com/1040669
Commit-Queue: Vincent Belliard <vincent.belliard@arm.com>
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Cr-Commit-Position: refs/heads/master@{#52961}

src/wasm/baseline/arm64/liftoff-assembler-arm64.h

@@ -556,25 +556,37 @@ void LiftoffAssembler::emit_i32_set_cond(Condition cond, Register dst,
 }
 
 void LiftoffAssembler::emit_i64_eqz(Register dst, LiftoffRegister src) {
-  BAILOUT("emit_i64_eqz");
+  Cmp(src.gp().X(), xzr);
+  Cset(dst.W(), eq);
 }
 
 void LiftoffAssembler::emit_i64_set_cond(Condition cond, Register dst,
                                          LiftoffRegister lhs,
                                          LiftoffRegister rhs) {
-  BAILOUT("emit_i64_set_cond");
+  Cmp(lhs.gp().X(), rhs.gp().X());
+  Cset(dst.W(), cond);
 }
 
 void LiftoffAssembler::emit_f32_set_cond(Condition cond, Register dst,
                                          DoubleRegister lhs,
                                          DoubleRegister rhs) {
-  BAILOUT("emit_f32_set_cond");
+  Fcmp(lhs.S(), rhs.S());
+  Cset(dst.W(), cond);
+  if (cond != ne) {
+    // If V flag set, at least one of the arguments was a Nan -> false.
+    Csel(dst.W(), wzr, dst.W(), vs);
+  }
 }
 
 void LiftoffAssembler::emit_f64_set_cond(Condition cond, Register dst,
                                          DoubleRegister lhs,
                                          DoubleRegister rhs) {
-  BAILOUT("emit_f64_set_cond");
+  Fcmp(lhs.D(), rhs.D());
+  Cset(dst.W(), cond);
+  if (cond != ne) {
+    // If V flag set, at least one of the arguments was a Nan -> false.
+    Csel(dst.W(), wzr, dst.W(), vs);
+  }
 }
 
 void LiftoffAssembler::StackCheck(Label* ool_code) {