Commit dd5954bc authored by Junliang Yan's avatar Junliang Yan Committed by V8 LUCI CQ

PPC: move LoadXXX to TurboAssm

Change-Id: I1449424536b721e54f95aeb2e3b68fb25d6a5ccf
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2906033Reviewed-by: 's avatarMilad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#74676}
parent ea3ee6da
...@@ -2819,7 +2819,7 @@ void TurboAssembler::StoreWord(Register src, const MemOperand& mem, ...@@ -2819,7 +2819,7 @@ void TurboAssembler::StoreWord(Register src, const MemOperand& mem,
} }
} }
void MacroAssembler::LoadS16(Register dst, const MemOperand& mem, void TurboAssembler::LoadS16(Register dst, const MemOperand& mem,
Register scratch) { Register scratch) {
int offset = mem.offset(); int offset = mem.offset();
...@@ -2834,7 +2834,7 @@ void MacroAssembler::LoadS16(Register dst, const MemOperand& mem, ...@@ -2834,7 +2834,7 @@ void MacroAssembler::LoadS16(Register dst, const MemOperand& mem,
// Variable length depending on whether offset fits into immediate field // Variable length depending on whether offset fits into immediate field
// MemOperand currently only supports d-form // MemOperand currently only supports d-form
void MacroAssembler::LoadU16(Register dst, const MemOperand& mem, void TurboAssembler::LoadU16(Register dst, const MemOperand& mem,
Register scratch) { Register scratch) {
Register base = mem.ra(); Register base = mem.ra();
int offset = mem.offset(); int offset = mem.offset();
...@@ -2865,7 +2865,7 @@ void MacroAssembler::StoreHalfWord(Register src, const MemOperand& mem, ...@@ -2865,7 +2865,7 @@ void MacroAssembler::StoreHalfWord(Register src, const MemOperand& mem,
// Variable length depending on whether offset fits into immediate field // Variable length depending on whether offset fits into immediate field
// MemOperand currently only supports d-form // MemOperand currently only supports d-form
void MacroAssembler::LoadU8(Register dst, const MemOperand& mem, void TurboAssembler::LoadU8(Register dst, const MemOperand& mem,
Register scratch) { Register scratch) {
Register base = mem.ra(); Register base = mem.ra();
int offset = mem.offset(); int offset = mem.offset();
......
...@@ -711,6 +711,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { ...@@ -711,6 +711,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void DecompressAnyTagged(Register destination, Register source); void DecompressAnyTagged(Register destination, Register source);
void LoadU32(Register dst, const MemOperand& mem, Register scratch); void LoadU32(Register dst, const MemOperand& mem, Register scratch);
void LoadU16(Register dst, const MemOperand& mem, Register scratch = no_reg);
void LoadS16(Register dst, const MemOperand& mem, Register scratch = no_reg);
void LoadU8(Register dst, const MemOperand& mem, Register scratch);
void StoreWord(Register src, const MemOperand& mem, Register scratch); void StoreWord(Register src, const MemOperand& mem, Register scratch);
private: private:
...@@ -788,11 +791,8 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler { ...@@ -788,11 +791,8 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
// load a literal double value <value> to FPR <result> // load a literal double value <value> to FPR <result>
void LoadU16(Register dst, const MemOperand& mem, Register scratch = no_reg);
void LoadS16(Register dst, const MemOperand& mem, Register scratch = no_reg);
void StoreHalfWord(Register src, const MemOperand& mem, Register scratch); void StoreHalfWord(Register src, const MemOperand& mem, Register scratch);
void LoadU8(Register dst, const MemOperand& mem, Register scratch);
void StoreByte(Register src, const MemOperand& mem, Register scratch); void StoreByte(Register src, const MemOperand& mem, Register scratch);
void LoadDoubleU(DoubleRegister dst, const MemOperand& mem, void LoadDoubleU(DoubleRegister dst, const MemOperand& mem,
......
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