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Commit dd04f25b authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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PPC: [wasm-simd] Moving simd opcodes to the assembler header 


Change-Id: Ife10d7c8634cbd6b542dc522a49124f790f51921
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2216434Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#67992}
parent 966692e5
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Showing with 142 additions and 196 deletions
src/codegen/ppc/assembler-ppc.cc
View file @ dd04f25b
...@@ -1768,118 +1768,11 @@ void Assembler::mfvsrwz(const Register ra, const DoubleRegister rs) { ...@@ -1768,118 +1768,11 @@ void Assembler::mfvsrwz(const Register ra, const DoubleRegister rs) {
emit(MFVSRWZ | rs.code() * B21 | ra.code() * B16 | SX); emit(MFVSRWZ | rs.code() * B21 | ra.code() * B16 | SX);
} }
void Assembler::mtvsrd(const DoubleRegister rt, const Register ra) { void Assembler::mtvsrd(const Simd128Register rt, const Register ra) {
int TX = 1; int TX = 1;
emit(MTVSRD | rt.code() * B21 | ra.code() * B16 | TX); emit(MTVSRD | rt.code() * B21 | ra.code() * B16 | TX);
} }
void Assembler::vor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VOR | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vxor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VXOR | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vnor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VNOR | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsro(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VSRO | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vslo(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VSLO | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vperm(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb, const DoubleRegister rc) {
emit(VPERM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
rc.code() * B6);
}
void Assembler::vaddudm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDUDM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vadduwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDUWM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vadduhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDUHM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vaddubm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDUBM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vaddfp(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDFP | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsubfp(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBFP | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsubudm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBUDM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsubuwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBUWM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsubuhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBUHM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsububm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBUBM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vmuluwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VMULUWM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vpkuhum(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VPKUHUM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vmuleub(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VMULEUB | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vmuloub(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VMULOUB | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vmladduhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb, const Simd128Register rc) {
emit(VMLADDUHM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
rc.code() * B6);
}
// Pseudo instructions. // Pseudo instructions.
void Assembler::nop(int type) { void Assembler::nop(int type) {
Register reg = r0; Register reg = r0;
......
src/codegen/ppc/assembler-ppc.h
View file @ dd04f25b
...@@ -448,18 +448,44 @@ class Assembler : public AssemblerBase { ...@@ -448,18 +448,44 @@ class Assembler : public AssemblerBase {
#undef DECLARE_PPC_XX3_INSTRUCTIONS #undef DECLARE_PPC_XX3_INSTRUCTIONS
#define DECLARE_PPC_VX_INSTRUCTIONS_A_FORM(name, instr_name, instr_value) \ #define DECLARE_PPC_VX_INSTRUCTIONS_A_FORM(name, instr_name, instr_value) \
inline void name(const DoubleRegister rt, const DoubleRegister rb, \ inline void name(const Simd128Register rt, const Simd128Register rb, \
const Operand& imm) { \ const Operand& imm) { \
vx_form(instr_name, rt, rb, imm); \ vx_form(instr_name, rt, rb, imm); \
} }
#define DECLARE_PPC_VX_INSTRUCTIONS_B_FORM(name, instr_name, instr_value) \
inline void name(const Simd128Register rt, const Simd128Register ra, \
const Simd128Register rb) { \
vx_form(instr_name, rt, ra, rb); \
}
inline void vx_form(Instr instr, DoubleRegister rt, DoubleRegister rb, inline void vx_form(Instr instr, Simd128Register rt, Simd128Register rb,
const Operand& imm) { const Operand& imm) {
emit(instr | rt.code() * B21 | imm.immediate() * B16 | rb.code() * B11); emit(instr | rt.code() * B21 | imm.immediate() * B16 | rb.code() * B11);
} }
inline void vx_form(Instr instr, Simd128Register rt, Simd128Register ra,
Simd128Register rb) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
PPC_VX_OPCODE_A_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_A_FORM) PPC_VX_OPCODE_A_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_A_FORM)
PPC_VX_OPCODE_B_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_B_FORM)
#undef DECLARE_PPC_VX_INSTRUCTIONS_A_FORM #undef DECLARE_PPC_VX_INSTRUCTIONS_A_FORM
#undef DECLARE_PPC_VX_INSTRUCTIONS_B_FORM
#define DECLARE_PPC_VA_INSTRUCTIONS_A_FORM(name, instr_name, instr_value) \
inline void name(const Simd128Register rt, const Simd128Register ra, \
const Simd128Register rb, const Simd128Register rc) { \
va_form(instr_name, rt, ra, rb, rc); \
}
inline void va_form(Instr instr, Simd128Register rt, Simd128Register ra,
Simd128Register rb, Simd128Register rc) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
rc.code() * B6);
}
PPC_VA_OPCODE_A_FORM_LIST(DECLARE_PPC_VA_INSTRUCTIONS_A_FORM)
#undef DECLARE_PPC_VA_INSTRUCTIONS_A_FORM
RegList* GetScratchRegisterList() { return &scratch_register_list_; } RegList* GetScratchRegisterList() { return &scratch_register_list_; }
// --------------------------------------------------------------------------- // ---------------------------------------------------------------------------
...@@ -950,49 +976,7 @@ class Assembler : public AssemblerBase { ...@@ -950,49 +976,7 @@ class Assembler : public AssemblerBase {
// Vector instructions // Vector instructions
void mfvsrd(const Register ra, const DoubleRegister r); void mfvsrd(const Register ra, const DoubleRegister r);
void mfvsrwz(const Register ra, const DoubleRegister r); void mfvsrwz(const Register ra, const DoubleRegister r);
void mtvsrd(const DoubleRegister rt, const Register ra); void mtvsrd(const Simd128Register rt, const Register ra);
void vxor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vnor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vsro(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vslo(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vperm(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb, const DoubleRegister rc);
void vaddudm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vadduwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vadduhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vaddubm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vaddfp(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsubfp(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsubudm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsubuwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsubuhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsububm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vmuluwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vpkuhum(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vmuleub(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vmuloub(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vmladduhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb, const Simd128Register rc);
// Pseudo instructions // Pseudo instructions
......
src/codegen/ppc/constants-ppc.h
View file @ dd04f25b
...@@ -1920,7 +1920,13 @@ using Instr = uint32_t; ...@@ -1920,7 +1920,13 @@ using Instr = uint32_t;
/* Floating Reciprocal Square Root Estimate Single */ \ /* Floating Reciprocal Square Root Estimate Single */ \
V(frsqrtes, FRSQRTES, 0xEC000034) V(frsqrtes, FRSQRTES, 0xEC000034)
#define PPC_VA_OPCODE_LIST(V) \ #define PPC_VA_OPCODE_A_FORM_LIST(V) \
/* Vector Permute */ \
V(vperm, VPERM, 0x1000002B) \
/* Vector Multiply-Low-Add Unsigned Halfword Modulo */ \
V(vmladduhm, VMLADDUHM, 0x10000022)
#define PPC_VA_OPCODE_UNUSED_LIST(V) \
/* Vector Add Extended & write Carry Unsigned Quadword */ \ /* Vector Add Extended & write Carry Unsigned Quadword */ \
V(vaddecuq, VADDECUQ, 0x1000003D) \ V(vaddecuq, VADDECUQ, 0x1000003D) \
/* Vector Add Extended Unsigned Quadword Modulo */ \ /* Vector Add Extended Unsigned Quadword Modulo */ \
...@@ -1931,8 +1937,6 @@ using Instr = uint32_t; ...@@ -1931,8 +1937,6 @@ using Instr = uint32_t;
V(vmhaddshs, VMHADDSHS, 0x10000020) \ V(vmhaddshs, VMHADDSHS, 0x10000020) \
/* Vector Multiply-High-Round-Add Signed Halfword Saturate */ \ /* Vector Multiply-High-Round-Add Signed Halfword Saturate */ \
V(vmhraddshs, VMHRADDSHS, 0x10000021) \ V(vmhraddshs, VMHRADDSHS, 0x10000021) \
/* Vector Multiply-Low-Add Unsigned Halfword Modulo */ \
V(vmladduhm, VMLADDUHM, 0x10000022) \
/* Vector Multiply-Sum Mixed Byte Modulo */ \ /* Vector Multiply-Sum Mixed Byte Modulo */ \
V(vmsummbm, VMSUMMBM, 0x10000025) \ V(vmsummbm, VMSUMMBM, 0x10000025) \
/* Vector Multiply-Sum Signed Halfword Modulo */ \ /* Vector Multiply-Sum Signed Halfword Modulo */ \
...@@ -1947,8 +1951,6 @@ using Instr = uint32_t; ...@@ -1947,8 +1951,6 @@ using Instr = uint32_t;
V(vmsumuhs, VMSUMUHS, 0x10000027) \ V(vmsumuhs, VMSUMUHS, 0x10000027) \
/* Vector Negative Multiply-Subtract Single-Precision */ \ /* Vector Negative Multiply-Subtract Single-Precision */ \
V(vnmsubfp, VNMSUBFP, 0x1000002F) \ V(vnmsubfp, VNMSUBFP, 0x1000002F) \
/* Vector Permute */ \
V(vperm, VPERM, 0x1000002B) \
/* Vector Select */ \ /* Vector Select */ \
V(vsel, VSEL, 0x1000002A) \ V(vsel, VSEL, 0x1000002A) \
/* Vector Shift Left Double by Octet Immediate */ \ /* Vector Shift Left Double by Octet Immediate */ \
...@@ -1960,6 +1962,10 @@ using Instr = uint32_t; ...@@ -1960,6 +1962,10 @@ using Instr = uint32_t;
/* Vector Permute and Exclusive-OR */ \ /* Vector Permute and Exclusive-OR */ \
V(vpermxor, VPERMXOR, 0x1000002D) V(vpermxor, VPERMXOR, 0x1000002D)
#define PPC_VA_OPCODE_LIST(V) \
PPC_VA_OPCODE_A_FORM_LIST(V) \
PPC_VA_OPCODE_UNUSED_LIST(V)
#define PPC_XX1_OPCODE_LIST(V) \ #define PPC_XX1_OPCODE_LIST(V) \
/* Load VSR Scalar Doubleword Indexed */ \ /* Load VSR Scalar Doubleword Indexed */ \
V(lxsdx, LXSDX, 0x7C000498) \ V(lxsdx, LXSDX, 0x7C000498) \
...@@ -2200,6 +2206,46 @@ using Instr = uint32_t; ...@@ -2200,6 +2206,46 @@ using Instr = uint32_t;
/* Vector Splat Halfword */ \ /* Vector Splat Halfword */ \
V(vsplth, VSPLTH, 0x1000024C) V(vsplth, VSPLTH, 0x1000024C)
#define PPC_VX_OPCODE_B_FORM_LIST(V) \
/* Vector Logical OR */ \
V(vor, VOR, 0x10000484) \
/* Vector Logical XOR */ \
V(vxor, VXOR, 0x100004C4) \
/* Vector Logical NOR */ \
V(vnor, VNOR, 0x10000504) \
/* Vector Shift Right by Octet */ \
V(vsro, VSRO, 0x1000044C) \
/* Vector Shift Left by Octet */ \
V(vslo, VSLO, 0x1000040C) \
/* Vector Add Unsigned Doubleword Modulo */ \
V(vaddudm, VADDUDM, 0x100000C0) \
/* Vector Add Unsigned Word Modulo */ \
V(vadduwm, VADDUWM, 0x10000080) \
/* Vector Add Unsigned Halfword Modulo */ \
V(vadduhm, VADDUHM, 0x10000040) \
/* Vector Add Unsigned Byte Modulo */ \
V(vaddubm, VADDUBM, 0x10000000) \
/* Vector Add Single-Precision */ \
V(vaddfp, VADDFP, 0x1000000A) \
/* Vector Subtract Single-Precision */ \
V(vsubfp, VSUBFP, 0x1000004A) \
/* Vector Subtract Unsigned Doubleword Modulo */ \
V(vsubudm, VSUBUDM, 0x100004C0) \
/* Vector Subtract Unsigned Word Modulo */ \
V(vsubuwm, VSUBUWM, 0x10000480) \
/* Vector Subtract Unsigned Halfword Modulo */ \
V(vsubuhm, VSUBUHM, 0x10000440) \
/* Vector Subtract Unsigned Byte Modulo */ \
V(vsububm, VSUBUBM, 0x10000400) \
/* Vector Multiply Unsigned Word Modulo */ \
V(vmuluwm, VMULUWM, 0x10000089) \
/* Vector Pack Unsigned Halfword Unsigned Modulo */ \
V(vpkuhum, VPKUHUM, 0x1000000E) \
/* Vector Multiply Even Unsigned Byte */ \
V(vmuleub, VMULEUB, 0x10000208) \
/* Vector Multiply Odd Unsigned Byte */ \
V(vmuloub, VMULOUB, 0x10000008)
#define PPC_VX_OPCODE_UNUSED_LIST(V) \ #define PPC_VX_OPCODE_UNUSED_LIST(V) \
/* Decimal Add Modulo */ \ /* Decimal Add Modulo */ \
V(bcdadd, BCDADD, 0xF0000400) \ V(bcdadd, BCDADD, 0xF0000400) \
...@@ -2213,28 +2259,18 @@ using Instr = uint32_t; ...@@ -2213,28 +2259,18 @@ using Instr = uint32_t;
V(vaddcuq, VADDCUQ, 0x10000140) \ V(vaddcuq, VADDCUQ, 0x10000140) \
/* Vector Add and Write Carry-Out Unsigned Word */ \ /* Vector Add and Write Carry-Out Unsigned Word */ \
V(vaddcuw, VADDCUW, 0x10000180) \ V(vaddcuw, VADDCUW, 0x10000180) \
/* Vector Add Single-Precision */ \
V(vaddfp, VADDFP, 0x1000000A) \
/* Vector Add Signed Byte Saturate */ \ /* Vector Add Signed Byte Saturate */ \
V(vaddsbs, VADDSBS, 0x10000300) \ V(vaddsbs, VADDSBS, 0x10000300) \
/* Vector Add Signed Halfword Saturate */ \ /* Vector Add Signed Halfword Saturate */ \
V(vaddshs, VADDSHS, 0x10000340) \ V(vaddshs, VADDSHS, 0x10000340) \
/* Vector Add Signed Word Saturate */ \ /* Vector Add Signed Word Saturate */ \
V(vaddsws, VADDSWS, 0x10000380) \ V(vaddsws, VADDSWS, 0x10000380) \
/* Vector Add Unsigned Byte Modulo */ \
V(vaddubm, VADDUBM, 0x10000000) \
/* Vector Add Unsigned Byte Saturate */ \ /* Vector Add Unsigned Byte Saturate */ \
V(vaddubs, VADDUBS, 0x10000200) \ V(vaddubs, VADDUBS, 0x10000200) \
/* Vector Add Unsigned Doubleword Modulo */ \
V(vaddudm, VADDUDM, 0x100000C0) \
/* Vector Add Unsigned Halfword Modulo */ \
V(vadduhm, VADDUHM, 0x10000040) \
/* Vector Add Unsigned Halfword Saturate */ \ /* Vector Add Unsigned Halfword Saturate */ \
V(vadduhs, VADDUHS, 0x10000240) \ V(vadduhs, VADDUHS, 0x10000240) \
/* Vector Add Unsigned Quadword Modulo */ \ /* Vector Add Unsigned Quadword Modulo */ \
V(vadduqm, VADDUQM, 0x10000100) \ V(vadduqm, VADDUQM, 0x10000100) \
/* Vector Add Unsigned Word Modulo */ \
V(vadduwm, VADDUWM, 0x10000080) \
/* Vector Add Unsigned Word Saturate */ \ /* Vector Add Unsigned Word Saturate */ \
V(vadduws, VADDUWS, 0x10000280) \ V(vadduws, VADDUWS, 0x10000280) \
/* Vector Logical AND */ \ /* Vector Logical AND */ \
...@@ -2333,8 +2369,6 @@ using Instr = uint32_t; ...@@ -2333,8 +2369,6 @@ using Instr = uint32_t;
V(vmulesh, VMULESH, 0x10000348) \ V(vmulesh, VMULESH, 0x10000348) \
/* Vector Multiply Even Signed Word */ \ /* Vector Multiply Even Signed Word */ \
V(vmulesw, VMULESW, 0x10000388) \ V(vmulesw, VMULESW, 0x10000388) \
/* Vector Multiply Even Unsigned Byte */ \
V(vmuleub, VMULEUB, 0x10000208) \
/* Vector Multiply Even Unsigned Halfword */ \ /* Vector Multiply Even Unsigned Halfword */ \
V(vmuleuh, VMULEUH, 0x10000248) \ V(vmuleuh, VMULEUH, 0x10000248) \
/* Vector Multiply Even Unsigned Word */ \ /* Vector Multiply Even Unsigned Word */ \
...@@ -2345,20 +2379,12 @@ using Instr = uint32_t; ...@@ -2345,20 +2379,12 @@ using Instr = uint32_t;
V(vmulosh, VMULOSH, 0x10000148) \ V(vmulosh, VMULOSH, 0x10000148) \
/* Vector Multiply Odd Signed Word */ \ /* Vector Multiply Odd Signed Word */ \
V(vmulosw, VMULOSW, 0x10000188) \ V(vmulosw, VMULOSW, 0x10000188) \
/* Vector Multiply Odd Unsigned Byte */ \
V(vmuloub, VMULOUB, 0x10000008) \
/* Vector Multiply Odd Unsigned Halfword */ \ /* Vector Multiply Odd Unsigned Halfword */ \
V(vmulouh, VMULOUH, 0x10000048) \ V(vmulouh, VMULOUH, 0x10000048) \
/* Vector Multiply Odd Unsigned Word */ \ /* Vector Multiply Odd Unsigned Word */ \
V(vmulouw, VMULOUW, 0x10000088) \ V(vmulouw, VMULOUW, 0x10000088) \
/* Vector Multiply Unsigned Word Modulo */ \
V(vmuluwm, VMULUWM, 0x10000089) \
/* Vector NAND */ \ /* Vector NAND */ \
V(vnand, VNAND, 0x10000584) \ V(vnand, VNAND, 0x10000584) \
/* Vector Logical NOR */ \
V(vnor, VNOR, 0x10000504) \
/* Vector Logical OR */ \
V(vor, VOR, 0x10000484) \
/* Vector OR with Complement */ \ /* Vector OR with Complement */ \
V(vorc, VORC, 0x10000544) \ V(vorc, VORC, 0x10000544) \
/* Vector Pack Pixel */ \ /* Vector Pack Pixel */ \
...@@ -2379,8 +2405,6 @@ using Instr = uint32_t; ...@@ -2379,8 +2405,6 @@ using Instr = uint32_t;
V(vpkudum, VPKUDUM, 0x1000044E) \ V(vpkudum, VPKUDUM, 0x1000044E) \
/* Vector Pack Unsigned Doubleword Unsigned Saturate */ \ /* Vector Pack Unsigned Doubleword Unsigned Saturate */ \
V(vpkudus, VPKUDUS, 0x100004CE) \ V(vpkudus, VPKUDUS, 0x100004CE) \
/* Vector Pack Unsigned Halfword Unsigned Modulo */ \
V(vpkuhum, VPKUHUM, 0x1000000E) \
/* Vector Pack Unsigned Halfword Unsigned Saturate */ \ /* Vector Pack Unsigned Halfword Unsigned Saturate */ \
V(vpkuhus, VPKUHUS, 0x1000008E) \ V(vpkuhus, VPKUHUS, 0x1000008E) \
/* Vector Pack Unsigned Word Unsigned Modulo */ \ /* Vector Pack Unsigned Word Unsigned Modulo */ \
...@@ -2431,8 +2455,6 @@ using Instr = uint32_t; ...@@ -2431,8 +2455,6 @@ using Instr = uint32_t;
V(vsld, VSLD, 0x100005C4) \ V(vsld, VSLD, 0x100005C4) \
/* Vector Shift Left Halfword */ \ /* Vector Shift Left Halfword */ \
V(vslh, VSLH, 0x10000144) \ V(vslh, VSLH, 0x10000144) \
/* Vector Shift Left by Octet */ \
V(vslo, VSLO, 0x1000040C) \
/* Vector Shift Left Word */ \ /* Vector Shift Left Word */ \
V(vslw, VSLW, 0x10000184) \ V(vslw, VSLW, 0x10000184) \
/* Vector Splat Immediate Signed Byte */ \ /* Vector Splat Immediate Signed Byte */ \
...@@ -2457,36 +2479,24 @@ using Instr = uint32_t; ...@@ -2457,36 +2479,24 @@ using Instr = uint32_t;
V(vsrd, VSRD, 0x100006C4) \ V(vsrd, VSRD, 0x100006C4) \
/* Vector Shift Right Halfword */ \ /* Vector Shift Right Halfword */ \
V(vsrh, VSRH, 0x10000244) \ V(vsrh, VSRH, 0x10000244) \
/* Vector Shift Right by Octet */ \
V(vsro, VSRO, 0x1000044C) \
/* Vector Shift Right Word */ \ /* Vector Shift Right Word */ \
V(vsrw, VSRW, 0x10000284) \ V(vsrw, VSRW, 0x10000284) \
/* Vector Subtract & write Carry Unsigned Quadword */ \ /* Vector Subtract & write Carry Unsigned Quadword */ \
V(vsubcuq, VSUBCUQ, 0x10000540) \ V(vsubcuq, VSUBCUQ, 0x10000540) \
/* Vector Subtract and Write Carry-Out Unsigned Word */ \ /* Vector Subtract and Write Carry-Out Unsigned Word */ \
V(vsubcuw, VSUBCUW, 0x10000580) \ V(vsubcuw, VSUBCUW, 0x10000580) \
/* Vector Subtract Single-Precision */ \
V(vsubfp, VSUBFP, 0x1000004A) \
/* Vector Subtract Signed Byte Saturate */ \ /* Vector Subtract Signed Byte Saturate */ \
V(vsubsbs, VSUBSBS, 0x10000700) \ V(vsubsbs, VSUBSBS, 0x10000700) \
/* Vector Subtract Signed Halfword Saturate */ \ /* Vector Subtract Signed Halfword Saturate */ \
V(vsubshs, VSUBSHS, 0x10000740) \ V(vsubshs, VSUBSHS, 0x10000740) \
/* Vector Subtract Signed Word Saturate */ \ /* Vector Subtract Signed Word Saturate */ \
V(vsubsws, VSUBSWS, 0x10000780) \ V(vsubsws, VSUBSWS, 0x10000780) \
/* Vector Subtract Unsigned Byte Modulo */ \
V(vsububm, VSUBUBM, 0x10000400) \
/* Vector Subtract Unsigned Byte Saturate */ \ /* Vector Subtract Unsigned Byte Saturate */ \
V(vsububs, VSUBUBS, 0x10000600) \ V(vsububs, VSUBUBS, 0x10000600) \
/* Vector Subtract Unsigned Doubleword Modulo */ \
V(vsubudm, VSUBUDM, 0x100004C0) \
/* Vector Subtract Unsigned Halfword Modulo */ \
V(vsubuhm, VSUBUHM, 0x10000440) \
/* Vector Subtract Unsigned Halfword Saturate */ \ /* Vector Subtract Unsigned Halfword Saturate */ \
V(vsubuhs, VSUBUHS, 0x10000640) \ V(vsubuhs, VSUBUHS, 0x10000640) \
/* Vector Subtract Unsigned Quadword Modulo */ \ /* Vector Subtract Unsigned Quadword Modulo */ \
V(vsubuqm, VSUBUQM, 0x10000500) \ V(vsubuqm, VSUBUQM, 0x10000500) \
/* Vector Subtract Unsigned Word Modulo */ \
V(vsubuwm, VSUBUWM, 0x10000480) \
/* Vector Subtract Unsigned Word Saturate */ \ /* Vector Subtract Unsigned Word Saturate */ \
V(vsubuws, VSUBUWS, 0x10000680) \ V(vsubuws, VSUBUWS, 0x10000680) \
/* Vector Sum across Half Signed Word Saturate */ \ /* Vector Sum across Half Signed Word Saturate */ \
...@@ -2515,8 +2525,6 @@ using Instr = uint32_t; ...@@ -2515,8 +2525,6 @@ using Instr = uint32_t;
V(vupklsh, VUPKLSH, 0x100002CE) \ V(vupklsh, VUPKLSH, 0x100002CE) \
/* Vector Unpack Low Signed Word */ \ /* Vector Unpack Low Signed Word */ \
V(vupklsw, VUPKLSW, 0x100006CE) \ V(vupklsw, VUPKLSW, 0x100006CE) \
/* Vector Logical XOR */ \
V(vxor, VXOR, 0x100004C4) \
/* Vector AES Cipher */ \ /* Vector AES Cipher */ \
V(vcipher, VCIPHER, 0x10000508) \ V(vcipher, VCIPHER, 0x10000508) \
/* Vector AES Cipher Last */ \ /* Vector AES Cipher Last */ \
...@@ -2538,6 +2546,7 @@ using Instr = uint32_t; ...@@ -2538,6 +2546,7 @@ using Instr = uint32_t;
#define PPC_VX_OPCODE_LIST(V) \ #define PPC_VX_OPCODE_LIST(V) \
PPC_VX_OPCODE_A_FORM_LIST(V) \ PPC_VX_OPCODE_A_FORM_LIST(V) \
PPC_VX_OPCODE_B_FORM_LIST(V) \
PPC_VX_OPCODE_UNUSED_LIST(V) PPC_VX_OPCODE_UNUSED_LIST(V)
#define PPC_XS_OPCODE_LIST(V) \ #define PPC_XS_OPCODE_LIST(V) \
......
src/diagnostics/ppc/disasm-ppc.cc
View file @ dd04f25b
...@@ -364,6 +364,10 @@ void Decoder::DecodeExt0(Instruction* instr) { ...@@ -364,6 +364,10 @@ void Decoder::DecodeExt0(Instruction* instr) {
Format(instr, "vperm 'Dt, 'Da, 'Db, 'Dc"); Format(instr, "vperm 'Dt, 'Da, 'Db, 'Dc");
return; return;
} }
case VMLADDUHM: {
Format(instr, "vmladduhm 'Dt, 'Da, 'Db, 'Dc");
return;
}
} }
switch (EXT0 | (instr->BitField(10, 0))) { switch (EXT0 | (instr->BitField(10, 0))) {
case VSPLTB: { case VSPLTB: {
...@@ -398,6 +402,62 @@ void Decoder::DecodeExt0(Instruction* instr) { ...@@ -398,6 +402,62 @@ void Decoder::DecodeExt0(Instruction* instr) {
Format(instr, "vslo 'Dt, 'Da, 'Db"); Format(instr, "vslo 'Dt, 'Da, 'Db");
break; break;
} }
case VADDUDM: {
Format(instr, "vaddudm 'Dt, 'Da, 'Db");
break;
}
case VADDUWM: {
Format(instr, "vadduwm 'Dt, 'Da, 'Db");
break;
}
case VADDUHM: {
Format(instr, "vadduhm 'Dt, 'Da, 'Db");
break;
}
case VADDUBM: {
Format(instr, "vaddubm 'Dt, 'Da, 'Db");
break;
}
case VADDFP: {
Format(instr, "vaddfp 'Dt, 'Da, 'Db");
break;
}
case VSUBFP: {
Format(instr, "vsubfp 'Dt, 'Da, 'Db");
break;
}
case VSUBUDM: {
Format(instr, "vsubudm 'Dt, 'Da, 'Db");
break;
}
case VSUBUWM: {
Format(instr, "vsubuwm 'Dt, 'Da, 'Db");
break;
}
case VSUBUHM: {
Format(instr, "vsubuhm 'Dt, 'Da, 'Db");
break;
}
case VSUBUBM: {
Format(instr, "vsububm 'Dt, 'Da, 'Db");
break;
}
case VMULUWM: {
Format(instr, "vmuluwm 'Dt, 'Da, 'Db");
break;
}
case VPKUHUM: {
Format(instr, "vpkuhum 'Dt, 'Da, 'Db");
break;
}
case VMULEUB: {
Format(instr, "vmuleub 'Dt, 'Da, 'Db");
break;
}
case VMULOUB: {
Format(instr, "vmuloub 'Dt, 'Da, 'Db");
break;
}
} }
} }
......
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