s390: fix dcheck failures on debug

Change-Id: Ie950a24612949f2f5ab96d2fd5d681f817fdde46
Reviewed-on: https://chromium-review.googlesource.com/1151867
Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
Reviewed-by: John Barboza <jbarboza@ca.ibm.com>
Reviewed-by: Joran Siu <joransiu@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#54734}

src/s390/assembler-s390.h

@@ -980,7 +980,7 @@ enum FIDBRA_FLAGS {
 
 inline void rsi_format(Opcode op, int f1, int f2, int f3) {
   DCHECK(is_uint8(op));
-  DCHECK(is_uint16(f3));
+  DCHECK(is_uint16(f3) || is_int16(f3));
   uint32_t code = getfield<uint32_t, 4, 0, 8>(op) |
                   getfield<uint32_t, 4, 8, 12>(f1) |
                   getfield<uint32_t, 4, 12, 16>(f2) |
@@ -1074,7 +1074,7 @@ inline void si_format(Opcode op, int f1, int f2, int f3) {
 inline void siy_format(Opcode op, int f1, int f2, int f3) {
   DCHECK(is_uint20(f3) || is_int20(f3));
   DCHECK(is_uint16(op));
-  DCHECK(is_uint8(f1));
+  DCHECK(is_uint8(f1) || is_int8(f1));
   uint64_t code = getfield<uint64_t, 6, 0, 8>(op >> 8) |
                   getfield<uint64_t, 6, 8, 16>(f1) |
                   getfield<uint64_t, 6, 16, 20>(f2) |

src/s390/macro-assembler-s390.cc

@@ -953,7 +953,7 @@ void TurboAssembler::ShiftRightPair(Register dst_low, Register dst_high,
                                     uint32_t shift) {
   LoadRR(r0, src_high);
   LoadRR(r1, src_low);
-  srdl(r0, r0, Operand(shift));
+  srdl(r0, Operand(shift));
   LoadRR(dst_high, r0);
   LoadRR(dst_low, r1);
 }
@@ -2236,7 +2236,7 @@ void TurboAssembler::Div32(Register dst, Register src1, Register src2) {
 #define Generate_DivU32(instr) \
   {                            \
     lr(r0, src1);              \
-    srdl(r0, r0, Operand(32)); \
+    srdl(r0, Operand(32)); \
     instr(r0, src2);           \
     LoadlW(dst, r1);           \
   }
@@ -2310,7 +2310,7 @@ void TurboAssembler::Mod32(Register dst, Register src1, Register src2) {
 #define Generate_ModU32(instr) \
   {                            \
     lr(r0, src1);              \
-    srdl(r0, r0, Operand(32)); \
+    srdl(r0, Operand(32)); \
     instr(r0, src2);           \
     LoadlW(dst, r0);           \
   }