[mips][Liftoff] Implement i64 shift with immediate

port 42e8c231 https://crrev.com/c/1899770

Original Commit Message:

  [Liftoff] Implement i64 shift with immediate

  Especially on ia32 and x64, shifts with immediate generate much shorter
  and more efficient code.

Change-Id: Ia7f20db8e3ed88efe8c09e4afc9dbadc8e3b0362
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1903289
Auto-Submit: Zhao Jiazhong <kyslie3100@gmail.com>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64838}

src/codegen/mips/macro-assembler-mips.cc

@@ -1562,12 +1562,12 @@ void TurboAssembler::ShlPair(Register dst_low, Register dst_high,
                              uint32_t shift, Register scratch) {
   shift = shift & 0x3F;
   if (shift == 0) {
-    mov(dst_low, src_low);
     mov(dst_high, src_high);
+    mov(dst_low, src_low);
   } else if (shift < 32) {
     if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
-      srl(dst_high, src_low, 32 - shift);
       Ins(dst_high, src_high, shift, 32 - shift);
+      srl(dst_high, src_low, 32 - shift);
       sll(dst_low, src_low, shift);
     } else {
       sll(dst_high, src_high, shift);
@@ -1624,8 +1624,8 @@ void TurboAssembler::ShrPair(Register dst_low, Register dst_high,
       Ins(dst_low, src_high, 32 - shift, shift);
       srl(dst_high, src_high, shift);
     } else {
-      srl(dst_high, src_high, shift);
       srl(dst_low, src_low, shift);
+      srl(dst_high, src_high, shift);
       shift = 32 - shift;
       sll(scratch, src_high, shift);
       Or(dst_low, dst_low, scratch);
@@ -1674,8 +1674,8 @@ void TurboAssembler::SarPair(Register dst_low, Register dst_high,
       Ins(dst_low, src_high, 32 - shift, shift);
       sra(dst_high, src_high, shift);
     } else {
-      sra(dst_high, src_high, shift);
       srl(dst_low, src_low, shift);
+      sra(dst_high, src_high, shift);
       shift = 32 - shift;
       sll(scratch, src_high, shift);
       Or(dst_low, dst_low, scratch);

src/wasm/baseline/mips/liftoff-assembler-mips.h

@@ -135,6 +135,18 @@ inline void push(LiftoffAssembler* assm, LiftoffRegister reg, ValueType type) {
   }
 }
 
+inline Register EnsureNoAlias(Assembler* assm, Register reg,
+                              LiftoffRegister must_not_alias,
+                              UseScratchRegisterScope* temps) {
+  if (reg != must_not_alias.low_gp() && reg != must_not_alias.high_gp())
+    return reg;
+  Register tmp = temps->Acquire();
+  DCHECK_NE(must_not_alias.low_gp(), tmp);
+  DCHECK_NE(must_not_alias.high_gp(), tmp);
+  assm->movz(tmp, reg, zero_reg);
+  return tmp;
+}
+
 #if defined(V8_TARGET_BIG_ENDIAN)
 inline void ChangeEndiannessLoad(LiftoffAssembler* assm, LiftoffRegister dst,
                                  LoadType type, LiftoffRegList pinned) {
@@ -845,12 +857,36 @@ void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
                                    &TurboAssembler::ShlPair);
 }
 
+void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
+                                    int32_t amount) {
+  UseScratchRegisterScope temps(this);
+  // {src.low_gp()} will still be needed after writing {dst.high_gp()}.
+  Register src_low = liftoff::EnsureNoAlias(this, src.low_gp(), dst, &temps);
+  DCHECK_NE(dst.low_gp(), kScratchReg);
+  DCHECK_NE(dst.high_gp(), kScratchReg);
+
+  ShlPair(dst.low_gp(), dst.high_gp(), src_low, src.high_gp(), amount,
+          kScratchReg);
+}
+
 void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
                                     Register amount) {
   liftoff::Emit64BitShiftOperation(this, dst, src, amount,
                                    &TurboAssembler::SarPair);
 }
 
+void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
+                                    int32_t amount) {
+  UseScratchRegisterScope temps(this);
+  // {src.high_gp()} will still be needed after writing {dst.low_gp()}.
+  Register src_high = liftoff::EnsureNoAlias(this, src.high_gp(), dst, &temps);
+  DCHECK_NE(dst.low_gp(), kScratchReg);
+  DCHECK_NE(dst.high_gp(), kScratchReg);
+
+  SarPair(dst.low_gp(), dst.high_gp(), src.low_gp(), src_high, amount,
+          kScratchReg);
+}
+
 void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
                                     Register amount) {
   liftoff::Emit64BitShiftOperation(this, dst, src, amount,
@@ -858,9 +894,14 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
 }
 
 void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
-                                    int amount) {
-  DCHECK(is_uint6(amount));
-  ShrPair(dst.high_gp(), dst.low_gp(), src.high_gp(), src.low_gp(), amount,
+                                    int32_t amount) {
+  UseScratchRegisterScope temps(this);
+  // {src.high_gp()} will still be needed after writing {dst.low_gp()}.
+  Register src_high = liftoff::EnsureNoAlias(this, src.high_gp(), dst, &temps);
+  DCHECK_NE(dst.low_gp(), kScratchReg);
+  DCHECK_NE(dst.high_gp(), kScratchReg);
+
+  ShrPair(dst.low_gp(), dst.high_gp(), src.low_gp(), src_high, amount,
           kScratchReg);
 }
 

src/wasm/baseline/mips64/liftoff-assembler-mips64.h

@@ -766,8 +766,8 @@ I64_BINOP_I(xor, Xor)
     instruction(dst.gp(), src.gp(), amount);                                \
   }
 
-I64_SHIFTOP(shl, dsllv)
-I64_SHIFTOP(sar, dsrav)
+I64_SHIFTOP_I(shl, dsll)
+I64_SHIFTOP_I(sar, dsra)
 I64_SHIFTOP_I(shr, dsrl)
 
 #undef I64_SHIFTOP