Skip to content

V
V8
Commit c62e4f2d authored by alph's avatar alph Committed by Commit bot
Browse files
Options

[x64] Refactor AVX instructions declarations. 

BUG=v8:4406
LOG=N

Review URL: https://codereview.chromium.org/1415463004

Cr-Commit-Position: refs/heads/master@{#31394}
parent 063e2316
Hide whitespace changes
Inline Side-by-side
Showing with 48 additions and 109 deletions
src/x64/assembler-x64.h
View file @ c62e4f2d
...@@ -1297,54 +1297,48 @@ class Assembler : public AssemblerBase { ...@@ -1297,54 +1297,48 @@ class Assembler : public AssemblerBase {
void vmovsd(const Operand& dst, XMMRegister src) { void vmovsd(const Operand& dst, XMMRegister src) {
vsd(0x11, src, xmm0, dst); vsd(0x11, src, xmm0, dst);
} }
void vaddsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsd(0x58, dst, src1, src2); #define AVX_SP_3(instr, opcode) \
} AVX_S_3(instr, opcode) \
void vaddsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { AVX_P_3(instr, opcode)
vsd(0x58, dst, src1, src2);
} #define AVX_S_3(instr, opcode) \
void vsubsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { AVX_3(instr##ss, opcode, vss) \
vsd(0x5c, dst, src1, src2); AVX_3(instr##sd, opcode, vsd)
}
void vsubsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { #define AVX_P_3(instr, opcode) \
vsd(0x5c, dst, src1, src2); AVX_3(instr##ps, opcode, vps) \
} AVX_3(instr##pd, opcode, vpd)
void vmulsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsd(0x59, dst, src1, src2); #define AVX_3(instr, opcode, impl) \
} void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
void vmulsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { impl(opcode, dst, src1, src2); \
vsd(0x59, dst, src1, src2); } \
} void instr(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
void vdivsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { impl(opcode, dst, src1, src2); \
vsd(0x5e, dst, src1, src2); }
}
void vdivsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { AVX_SP_3(vadd, 0x58);
vsd(0x5e, dst, src1, src2); AVX_SP_3(vsub, 0x5c);
} AVX_SP_3(vmul, 0x59);
void vmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { AVX_SP_3(vdiv, 0x5e);
vsd(0x5f, dst, src1, src2); AVX_SP_3(vmin, 0x5d);
} AVX_SP_3(vmax, 0x5f);
void vmaxsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { AVX_P_3(vand, 0x54);
vsd(0x5f, dst, src1, src2); AVX_P_3(vxor, 0x57);
} AVX_3(vcvtsd2ss, 0x5a, vsd);
void vminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsd(0x5d, dst, src1, src2); #undef AVX_3
} #undef AVX_S_3
void vminsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { #undef AVX_P_3
vsd(0x5d, dst, src1, src2); #undef AVX_SP_3
}
void vcvtss2sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { void vcvtss2sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsd(0x5a, dst, src1, src2, kF3, k0F, kWIG); vsd(0x5a, dst, src1, src2, kF3, k0F, kWIG);
} }
void vcvtss2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { void vcvtss2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vsd(0x5a, dst, src1, src2, kF3, k0F, kWIG); vsd(0x5a, dst, src1, src2, kF3, k0F, kWIG);
} }
void vcvtsd2ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsd(0x5a, dst, src1, src2);
}
void vcvtsd2ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vsd(0x5a, dst, src1, src2);
}
void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Register src2) { void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = {src2.code()}; XMMRegister isrc2 = {src2.code()};
vsd(0x2a, dst, src1, isrc2, kF2, k0F, kW0); vsd(0x2a, dst, src1, isrc2, kF2, k0F, kW0);
...@@ -1386,42 +1380,6 @@ class Assembler : public AssemblerBase { ...@@ -1386,42 +1380,6 @@ class Assembler : public AssemblerBase {
void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2, void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2,
SIMDPrefix pp, LeadingOpcode m, VexW w); SIMDPrefix pp, LeadingOpcode m, VexW w);
void vaddss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x58, dst, src1, src2);
}
void vaddss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vss(0x58, dst, src1, src2);
}
void vsubss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x5c, dst, src1, src2);
}
void vsubss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vss(0x5c, dst, src1, src2);
}
void vmulss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x59, dst, src1, src2);
}
void vmulss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vss(0x59, dst, src1, src2);
}
void vdivss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x5e, dst, src1, src2);
}
void vdivss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vss(0x5e, dst, src1, src2);
}
void vmaxss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x5f, dst, src1, src2);
}
void vmaxss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vss(0x5f, dst, src1, src2);
}
void vminss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x5d, dst, src1, src2);
}
void vminss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vss(0x5d, dst, src1, src2);
}
void vmovss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { void vmovss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x10, dst, src1, src2); vss(0x10, dst, src1, src2);
} }
...@@ -1436,6 +1394,18 @@ class Assembler : public AssemblerBase { ...@@ -1436,6 +1394,18 @@ class Assembler : public AssemblerBase {
void vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); void vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vmovaps(XMMRegister dst, XMMRegister src) { vps(0x28, dst, xmm0, src); }
void vmovapd(XMMRegister dst, XMMRegister src) { vpd(0x28, dst, xmm0, src); }
void vmovmskpd(Register dst, XMMRegister src) {
XMMRegister idst = {dst.code()};
vpd(0x50, idst, xmm0, src);
}
void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
// BMI instruction // BMI instruction
void andnq(Register dst, Register src1, Register src2) { void andnq(Register dst, Register src1, Register src2) {
bmi1q(0xf2, dst, src1, src2); bmi1q(0xf2, dst, src1, src2);
...@@ -1613,37 +1583,6 @@ class Assembler : public AssemblerBase { ...@@ -1613,37 +1583,6 @@ class Assembler : public AssemblerBase {
void rorxl(Register dst, Register src, byte imm8); void rorxl(Register dst, Register src, byte imm8);
void rorxl(Register dst, const Operand& src, byte imm8); void rorxl(Register dst, const Operand& src, byte imm8);
void vmovaps(XMMRegister dst, XMMRegister src) { vps(0x28, dst, xmm0, src); }
void vmovapd(XMMRegister dst, XMMRegister src) { vpd(0x28, dst, xmm0, src); }
void vmovmskpd(Register dst, XMMRegister src) {
XMMRegister idst = {dst.code()};
vpd(0x50, idst, xmm0, src);
}
#define PACKED_OP_LIST(V) \
V(and, 0x54) \
V(xor, 0x57)
#define AVX_PACKED_OP_DECLARE(name, opcode) \
void v##name##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vps(opcode, dst, src1, src2); \
} \
void v##name##ps(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vps(opcode, dst, src1, src2); \
} \
void v##name##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vpd(opcode, dst, src1, src2); \
} \
void v##name##pd(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vpd(opcode, dst, src1, src2); \
}
PACKED_OP_LIST(AVX_PACKED_OP_DECLARE);
void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
// Debugging // Debugging
void Print(); void Print();
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment