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Commit c4906f6e authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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s390: [wasm-simd] Implement simd shift and bitwise operations 

Change-Id: Id9f40ac278c5a25739b11d3af06de1f7052d1c67
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2015943Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#65951}
parent d9cb964e
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Showing with 166 additions and 29 deletions
src/compiler/backend/s390/code-generator-s390.cc
View file @ c4906f6e
......@@ -3332,6 +3332,94 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
kScratchDoubleReg, Condition(0), Condition(0), Condition(0));
break;
}
// vector shifts
#define VECTOR_SHIFT(op, mode) \
{ \
__ vlvg(kScratchDoubleReg, i.InputRegister(1), MemOperand(r0, 0), \
Condition(mode)); \
__ vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), \
Condition(mode)); \
__ op(i.OutputSimd128Register(), i.InputSimd128Register(0), \
kScratchDoubleReg, Condition(0), Condition(0), Condition(mode)); \
}
case kS390_I32x4Shl: {
VECTOR_SHIFT(veslv, 2);
break;
}
case kS390_I32x4ShrS: {
VECTOR_SHIFT(vesrav, 2);
break;
}
case kS390_I32x4ShrU: {
VECTOR_SHIFT(vesrlv, 2);
break;
}
case kS390_I16x8Shl: {
VECTOR_SHIFT(veslv, 1);
break;
}
case kS390_I16x8ShrS: {
VECTOR_SHIFT(vesrav, 1);
break;
}
case kS390_I16x8ShrU: {
VECTOR_SHIFT(vesrlv, 1);
break;
}
case kS390_I8x16Shl: {
VECTOR_SHIFT(veslv, 0);
break;
}
case kS390_I8x16ShrS: {
VECTOR_SHIFT(vesrav, 0);
break;
}
case kS390_I8x16ShrU: {
VECTOR_SHIFT(vesrlv, 0);
break;
}
// vector bitwise ops
case kS390_S128And: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
__ vn(dst, i.InputSimd128Register(0), src, Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_S128Or: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
__ vo(dst, i.InputSimd128Register(0), src, Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_S128Xor: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
__ vx(dst, i.InputSimd128Register(0), src, Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_S128Zero: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
__ vx(dst, dst, src, Condition(0), Condition(0), Condition(0));
break;
}
case kS390_S128Not: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
__ vno(dst, src, src, Condition(0), Condition(0), Condition(0));
break;
}
case kS390_S128Select: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register mask = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register src2 = i.InputSimd128Register(2);
__ vsel(dst, src1, src2, mask, Condition(0), Condition(0));
break;
}
default:
UNREACHABLE();
}
......
src/compiler/backend/s390/instruction-codes-s390.h
View file @ c4906f6e
......@@ -226,6 +226,9 @@ namespace compiler {
V(S390_I32x4GtU) \
V(S390_I32x4GeU) \
V(S390_I16x8Splat) \
V(S390_I32x4Shl) \
V(S390_I32x4ShrS) \
V(S390_I32x4ShrU) \
V(S390_I16x8ExtractLaneU) \
V(S390_I16x8ExtractLaneS) \
V(S390_I16x8ReplaceLane) \
......@@ -243,6 +246,9 @@ namespace compiler {
V(S390_I16x8GeS) \
V(S390_I16x8GtU) \
V(S390_I16x8GeU) \
V(S390_I16x8Shl) \
V(S390_I16x8ShrS) \
V(S390_I16x8ShrU) \
V(S390_I8x16Splat) \
V(S390_I8x16ExtractLaneU) \
V(S390_I8x16ExtractLaneS) \
......@@ -260,6 +266,15 @@ namespace compiler {
V(S390_I8x16GeS) \
V(S390_I8x16GtU) \
V(S390_I8x16GeU) \
V(S390_I8x16Shl) \
V(S390_I8x16ShrS) \
V(S390_I8x16ShrU) \
V(S390_S128And) \
V(S390_S128Or) \
V(S390_S128Xor) \
V(S390_S128Zero) \
V(S390_S128Not) \
V(S390_S128Select) \
V(S390_StoreSimd128) \
V(S390_LoadSimd128)
......
src/compiler/backend/s390/instruction-scheduler-s390.cc
View file @ c4906f6e
......@@ -171,6 +171,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I32x4GeS:
case kS390_I32x4GtU:
case kS390_I32x4GeU:
case kS390_I32x4Shl:
case kS390_I32x4ShrS:
case kS390_I32x4ShrU:
case kS390_I16x8Splat:
case kS390_I16x8ExtractLaneU:
case kS390_I16x8ExtractLaneS:
......@@ -189,6 +192,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I16x8GeS:
case kS390_I16x8GtU:
case kS390_I16x8GeU:
case kS390_I16x8Shl:
case kS390_I16x8ShrS:
case kS390_I16x8ShrU:
case kS390_I8x16Splat:
case kS390_I8x16ExtractLaneU:
case kS390_I8x16ExtractLaneS:
......@@ -206,6 +212,15 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I8x16GeS:
case kS390_I8x16GtU:
case kS390_I8x16GeU:
case kS390_I8x16Shl:
case kS390_I8x16ShrS:
case kS390_I8x16ShrU:
case kS390_S128And:
case kS390_S128Or:
case kS390_S128Xor:
case kS390_S128Zero:
case kS390_S128Not:
case kS390_S128Select:
return kNoOpcodeFlags;
case kS390_LoadWordS8:
......
src/compiler/backend/s390/instruction-selector-s390.cc
View file @ c4906f6e
......@@ -2566,7 +2566,23 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I8x16GtS) \
V(I8x16GeS) \
V(I8x16GtU) \
V(I8x16GeU)
V(I8x16GeU) \
V(S128And) \
V(S128Or) \
V(S128Xor)
#define SIMD_UNOP_LIST(V) V(S128Not)
#define SIMD_SHIFT_OPCODES(V) \
V(I32x4Shl) \
V(I32x4ShrS) \
V(I32x4ShrU) \
V(I16x8Shl) \
V(I16x8ShrS) \
V(I16x8ShrU) \
V(I8x16Shl) \
V(I8x16ShrS) \
V(I8x16ShrU)
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
......@@ -2615,22 +2631,43 @@ SIMD_TYPES(SIMD_VISIT_REPLACE_LANE)
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#undef SIMD_BINOP_LIST
#undef SIMD_TYPES
void InstructionSelector::VisitI32x4Shl(Node* node) { UNIMPLEMENTED(); }
#define SIMD_VISIT_UNOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0))); \
}
SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
#undef SIMD_VISIT_UNOP
#undef SIMD_UNOP_LIST
#define SIMD_VISIT_SHIFT(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1))); \
}
SIMD_SHIFT_OPCODES(SIMD_VISIT_SHIFT)
#undef SIMD_VISIT_SHIFT
#undef SIMD_SHIFT_OPCODES
#undef SIMD_TYPES
void InstructionSelector::VisitI32x4ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128Zero(Node* node) {
S390OperandGenerator g(this);
Emit(kS390_S128Zero, g.DefineAsRegister(node), g.DefineAsRegister(node));
}
void InstructionSelector::VisitI32x4ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128Select(Node* node) {
S390OperandGenerator g(this);
Emit(kS390_S128Select, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
g.UseRegister(node->InputAt(2)));
}
void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
......@@ -2675,18 +2712,8 @@ void InstructionSelector::VisitI8x16SubSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitS128And(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128Or(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128Xor(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128Not(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128Zero(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::EmitPrepareResults(
ZoneVector<PushParameter>* results, const CallDescriptor* call_descriptor,
Node* node) {
......@@ -2718,8 +2745,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128Select(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Abs(Node* node) { UNIMPLEMENTED(); }
......@@ -2805,12 +2830,6 @@ void InstructionSelector::VisitS1x16AnyTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16AllTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }
......
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