[riscv64][wasm-relaxed-simd] Implement relaxed i16x8.q15mulr_s

Port commit aaa15e65

Change-Id: I728d5f786c3e217d249bf6d356b2a004896ed582
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3844663
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Reviewed-by: Tobias Tebbi <tebbi@chromium.org>
Commit-Queue: Tobias Tebbi <tebbi@chromium.org>
Cr-Commit-Position: refs/heads/main@{#82617}

src/compiler/backend/instruction-selector.cc

@@ -2837,7 +2837,7 @@ void InstructionSelector::VisitI32x4RelaxedTruncF32x4U(Node* node) {
         // !V8_TARGET_ARCH_RISCV32
 
 #if !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_X64 && \
-    !V8_TARGET_ARCH_IA32
+    !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_RISCV64 && !V8_TARGET_ARCH_RISCV32
 void InstructionSelector::VisitI16x8RelaxedQ15MulRS(Node* node) {
   UNIMPLEMENTED();
 }

src/compiler/backend/riscv/instruction-selector-riscv.h

@@ -944,6 +944,7 @@ void InstructionSelector::VisitI16x8ExtAddPairwiseI8x16U(Node* node) {
   V(I16x8GeU, kRiscvI16x8GeU)                           \
   V(I16x8RoundingAverageU, kRiscvI16x8RoundingAverageU) \
   V(I16x8Q15MulRSatS, kRiscvI16x8Q15MulRSatS)           \
+  V(I16x8RelaxedQ15MulRS, kRiscvI16x8Q15MulRSatS)       \
   V(I16x8SConvertI32x4, kRiscvI16x8SConvertI32x4)       \
   V(I16x8UConvertI32x4, kRiscvI16x8UConvertI32x4)       \
   V(I8x16Add, kRiscvI8x16Add)                           \