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Commit bf8dae5b authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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s390: [wasm-simd] Implement simd conversion operations 

Change-Id: I6f7d3a5f123edea8674c0f9217b03760f3af016f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2028451Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#66059}
parent d6569052
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Showing with 87 additions and 27 deletions
src/compiler/backend/s390/code-generator-s390.cc
View file @ bf8dae5b
...@@ -3493,6 +3493,57 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3493,6 +3493,57 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vsel(dst, src1, src2, mask, Condition(0), Condition(0)); __ vsel(dst, src1, src2, mask, Condition(0), Condition(0));
break; break;
} }
// vector conversions
#define CONVERT_FLOAT_TO_INT32(convert) \
for (int index = 0; index < 4; index++) { \
__ vlgv(kScratchReg, kScratchDoubleReg, MemOperand(r0, index), \
Condition(2)); \
__ vlvg(kScratchDoubleReg, kScratchReg, MemOperand(r0, 0), Condition(2)); \
__ convert(kScratchReg, kScratchDoubleReg, kRoundToZero); \
__ vlvg(dst, kScratchReg, MemOperand(r0, index), Condition(2)); \
}
case kS390_I32x4SConvertF32x4: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
// NaN to 0
__ vlr(kScratchDoubleReg, src, Condition(0), Condition(0), Condition(0));
__ vfce(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
Condition(0), Condition(0), Condition(2));
__ vn(kScratchDoubleReg, src, kScratchDoubleReg, Condition(0),
Condition(0), Condition(0));
CONVERT_FLOAT_TO_INT32(ConvertFloat32ToInt32)
break;
}
case kS390_I32x4UConvertF32x4: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
// NaN to 0, negative to 0
__ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
Condition(0), Condition(0), Condition(0));
__ vfmax(kScratchDoubleReg, src, kScratchDoubleReg, Condition(1),
Condition(0), Condition(2));
CONVERT_FLOAT_TO_INT32(ConvertFloat32ToUnsignedInt32)
break;
}
#undef CONVERT_FLOAT_TO_INT32
#define CONVERT_INT32_TO_FLOAT(convert) \
Simd128Register src = i.InputSimd128Register(0); \
Simd128Register dst = i.OutputSimd128Register(); \
for (int index = 0; index < 4; index++) { \
__ vlgv(kScratchReg, src, MemOperand(r0, index), Condition(2)); \
__ convert(kScratchDoubleReg, kScratchReg); \
__ vlgv(kScratchReg, kScratchDoubleReg, MemOperand(r0, 0), Condition(2)); \
__ vlvg(dst, kScratchReg, MemOperand(r0, index), Condition(2)); \
}
case kS390_F32x4SConvertI32x4: {
CONVERT_INT32_TO_FLOAT(ConvertIntToFloat)
break;
}
case kS390_F32x4UConvertI32x4: {
CONVERT_INT32_TO_FLOAT(ConvertUnsignedIntToFloat)
break;
}
#undef CONVERT_INT32_TO_FLOAT
default: default:
UNREACHABLE(); UNREACHABLE();
} }
......
src/compiler/backend/s390/instruction-codes-s390.h
View file @ bf8dae5b
...@@ -234,6 +234,10 @@ namespace compiler { ...@@ -234,6 +234,10 @@ namespace compiler {
V(S390_I32x4Shl) \ V(S390_I32x4Shl) \
V(S390_I32x4ShrS) \ V(S390_I32x4ShrS) \
V(S390_I32x4ShrU) \ V(S390_I32x4ShrU) \
V(S390_I32x4SConvertF32x4) \
V(S390_I32x4UConvertF32x4) \
V(S390_F32x4SConvertI32x4) \
V(S390_F32x4UConvertI32x4) \
V(S390_I16x8ExtractLaneU) \ V(S390_I16x8ExtractLaneU) \
V(S390_I16x8ExtractLaneS) \ V(S390_I16x8ExtractLaneS) \
V(S390_I16x8ReplaceLane) \ V(S390_I16x8ReplaceLane) \
......
src/compiler/backend/s390/instruction-scheduler-s390.cc
View file @ bf8dae5b
...@@ -179,6 +179,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -179,6 +179,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I32x4ShrS: case kS390_I32x4ShrS:
case kS390_I32x4ShrU: case kS390_I32x4ShrU:
case kS390_I32x4Neg: case kS390_I32x4Neg:
case kS390_I32x4SConvertF32x4:
case kS390_I32x4UConvertF32x4:
case kS390_F32x4SConvertI32x4:
case kS390_F32x4UConvertI32x4:
case kS390_I16x8Splat: case kS390_I16x8Splat:
case kS390_I16x8ExtractLaneU: case kS390_I16x8ExtractLaneU:
case kS390_I16x8ExtractLaneS: case kS390_I16x8ExtractLaneS:
......
src/compiler/backend/s390/instruction-selector-s390.cc
View file @ bf8dae5b
...@@ -2581,15 +2581,15 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2581,15 +2581,15 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I8x16Neg) \ V(I8x16Neg) \
V(S128Not) V(S128Not)
#define SIMD_SHIFT_OPCODES(V) \ #define SIMD_SHIFT_LIST(V) \
V(I32x4Shl) \ V(I32x4Shl) \
V(I32x4ShrS) \ V(I32x4ShrS) \
V(I32x4ShrU) \ V(I32x4ShrU) \
V(I16x8Shl) \ V(I16x8Shl) \
V(I16x8ShrS) \ V(I16x8ShrS) \
V(I16x8ShrU) \ V(I16x8ShrU) \
V(I8x16Shl) \ V(I8x16Shl) \
V(I8x16ShrS) \ V(I8x16ShrS) \
V(I8x16ShrU) V(I8x16ShrU)
#define SIMD_BOOL_LIST(V) \ #define SIMD_BOOL_LIST(V) \
...@@ -2600,6 +2600,12 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2600,6 +2600,12 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(S1x8AllTrue) \ V(S1x8AllTrue) \
V(S1x16AllTrue) V(S1x16AllTrue)
#define SIMD_CONVERSION_LIST(V) \
V(I32x4SConvertF32x4) \
V(I32x4UConvertF32x4) \
V(F32x4SConvertI32x4) \
V(F32x4UConvertI32x4)
#define SIMD_VISIT_SPLAT(Type) \ #define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \ void InstructionSelector::Visit##Type##Splat(Node* node) { \
S390OperandGenerator g(this); \ S390OperandGenerator g(this); \
...@@ -2666,9 +2672,9 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP) ...@@ -2666,9 +2672,9 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
g.UseUniqueRegister(node->InputAt(0)), \ g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1))); \ g.UseUniqueRegister(node->InputAt(1))); \
} }
SIMD_SHIFT_OPCODES(SIMD_VISIT_SHIFT) SIMD_SHIFT_LIST(SIMD_VISIT_SHIFT)
#undef SIMD_VISIT_SHIFT #undef SIMD_VISIT_SHIFT
#undef SIMD_SHIFT_OPCODES #undef SIMD_SHIFT_LIST
#define SIMD_VISIT_BOOL(Opcode) \ #define SIMD_VISIT_BOOL(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \ void InstructionSelector::Visit##Opcode(Node* node) { \
...@@ -2679,6 +2685,17 @@ SIMD_SHIFT_OPCODES(SIMD_VISIT_SHIFT) ...@@ -2679,6 +2685,17 @@ SIMD_SHIFT_OPCODES(SIMD_VISIT_SHIFT)
} }
SIMD_BOOL_LIST(SIMD_VISIT_BOOL) SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
#undef SIMD_VISIT_BOOL #undef SIMD_VISIT_BOOL
#undef SIMD_BOOL_LIST
#define SIMD_VISIT_CONVERSION(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0))); \
}
SIMD_CONVERSION_LIST(SIMD_VISIT_CONVERSION)
#undef SIMD_VISIT_CONVERSION
#undef SIMD_CONVERSION_LIST
#undef SIMD_TYPES #undef SIMD_TYPES
void InstructionSelector::VisitS128Zero(Node* node) { void InstructionSelector::VisitS128Zero(Node* node) {
...@@ -2766,22 +2783,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); } ...@@ -2766,22 +2783,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4SConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitF32x4UConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4SConvertF32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) { void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
......
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