PPC: define liftoff cache registers

After https://crrev.com/c/2695401, CachRegs needed to be defined
on PPC to overwrite the default value "0xff".

The default value was causing the following failure on some tests:

```
#
# Fatal error in ../../src/wasm/baseline/liftoff-register.h, line 160
# Debug check failed: 0 != kLiftoffAssemblerGpCacheRegs & reg.bit()
  (0 vs. 0).
```

Values are taken from `src/execution/ppc/frame-constants-ppc.h`.

Change-Id: Idfc1d0fdc20d0b5aabc25e5b5809a93073a2dc3d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2698930Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#72827}

src/wasm/baseline/liftoff-assembler-defs.h

@@ -77,6 +77,14 @@ constexpr RegList kLiftoffAssemblerGpCacheRegs =
 constexpr RegList kLiftoffAssemblerFpCacheRegs = DoubleRegister::ListOf(
     d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12);
 
+#elif V8_TARGET_ARCH_PPC64
+
+constexpr RegList kLiftoffAssemblerGpCacheRegs =
+    Register::ListOf(r3, r4, r5, r6, r7, r8, r9, r10, r11);
+
+constexpr RegList kLiftoffAssemblerFpCacheRegs = DoubleRegister::ListOf(
+    d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12);
+
 #elif V8_TARGET_ARCH_RISCV64
 
 // Any change of kLiftoffAssemblerGpCacheRegs also need to update