Commit 81d4425e authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot

[wasm-simd] Implement integer absolute scalar lowering

Bug: v8:10233
Change-Id: I8bb564e595d5c2b093adea0b9dde9c1c86dcee70
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2084318Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66618}
parent 9423ede1
......@@ -113,6 +113,7 @@ void SimdScalarLowering::LowerGraph() {
V(I32x4LeU) \
V(I32x4GtU) \
V(I32x4GeU) \
V(I32x4Abs) \
V(S128And) \
V(S128Or) \
V(S128Xor) \
......@@ -186,7 +187,8 @@ void SimdScalarLowering::LowerGraph() {
V(I16x8LeS) \
V(I16x8LtU) \
V(I16x8LeU) \
V(I16x8RoundingAverageU)
V(I16x8RoundingAverageU) \
V(I16x8Abs)
#define FOREACH_INT8X16_OPCODE(V) \
V(I8x16Splat) \
......@@ -218,7 +220,8 @@ void SimdScalarLowering::LowerGraph() {
V(I8x16LeU) \
V(S8x16Swizzle) \
V(S8x16Shuffle) \
V(I8x16RoundingAverageU)
V(I8x16RoundingAverageU) \
V(I8x16Abs)
MachineType SimdScalarLowering::MachineTypeFrom(SimdType simdType) {
switch (simdType) {
......@@ -1238,6 +1241,30 @@ void SimdScalarLowering::LowerNode(Node* node) {
ReplaceNode(node, rep_node, num_lanes);
break;
}
case IrOpcode::kI32x4Abs:
case IrOpcode::kI16x8Abs:
case IrOpcode::kI8x16Abs: {
// From https://stackoverflow.com/a/14194764
// abs(x) = (x XOR y) - y
Node** rep = GetReplacementsWithType(node->InputAt(0), rep_type);
Node** rep_node = zone()->NewArray<Node*>(num_lanes);
for (int i = 0; i < num_lanes; ++i) {
// It's fine to shift by 31 even for i8x16 since each node is
// effectively expanded to 32 bits.
Node* y = graph()->NewNode(machine()->Word32Sar(), rep[i],
mcgraph_->Int32Constant(31));
rep_node[i] = graph()->NewNode(
machine()->Int32Sub(),
graph()->NewNode(machine()->Word32Xor(), rep[i], y), y);
if (node->opcode() == IrOpcode::kI16x8Neg) {
rep_node[i] = FixUpperBits(rep_node[i], kShift16);
} else if (node->opcode() == IrOpcode::kI8x16Neg) {
rep_node[i] = FixUpperBits(rep_node[i], kShift8);
}
}
ReplaceNode(node, rep_node, num_lanes);
break;
}
case IrOpcode::kS128Zero: {
DCHECK_EQ(0, node->InputCount());
Node* rep_node[kNumLanes32];
......
......@@ -1836,7 +1836,7 @@ WASM_SIMD_TEST(I32x4Neg) {
base::NegateWithWraparound);
}
WASM_SIMD_TEST_NO_LOWERING(I32x4Abs) {
WASM_SIMD_TEST(I32x4Abs) {
RunI32x4UnOpTest(execution_tier, lower_simd, kExprI32x4Abs, Abs);
}
......@@ -2099,7 +2099,7 @@ WASM_SIMD_TEST(I16x8Neg) {
base::NegateWithWraparound);
}
WASM_SIMD_TEST_NO_LOWERING(I16x8Abs) {
WASM_SIMD_TEST(I16x8Abs) {
RunI16x8UnOpTest(execution_tier, lower_simd, kExprI16x8Abs, Abs);
}
......@@ -2304,7 +2304,7 @@ WASM_SIMD_TEST(I8x16Neg) {
base::NegateWithWraparound);
}
WASM_SIMD_TEST_NO_LOWERING(I8x16Abs) {
WASM_SIMD_TEST(I8x16Abs) {
RunI8x16UnOpTest(execution_tier, lower_simd, kExprI8x16Abs, Abs);
}
......
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