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Commit 7290d15e authored by balazs.kilvady's avatar balazs.kilvady Committed by Commit bot
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MIPS: Improve naming of turbofan ops for %_DoubleHi, %_DoubleLo and %_ConstructDouble. 

BUG=

Review URL: https://codereview.chromium.org/1006523002

Cr-Commit-Position: refs/heads/master@{#27169}
parent 323ec9e8
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src/compiler/mips/code-generator-mips.cc
View file @ 7290d15e
......@@ -621,16 +621,16 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ Trunc_uw_d(i.InputDoubleRegister(0), i.OutputRegister(), scratch);
break;
}
case kMipsFmoveLowUwD:
case kMipsFloat64ExtractLowWord32:
__ FmoveLow(i.OutputRegister(), i.InputDoubleRegister(0));
break;
case kMipsFmoveLowDUw:
__ FmoveLow(i.OutputDoubleRegister(), i.InputRegister(1));
break;
case kMipsFmoveHighUwD:
case kMipsFloat64ExtractHighWord32:
__ FmoveHigh(i.OutputRegister(), i.InputDoubleRegister(0));
break;
case kMipsFmoveHighDUw:
case kMipsFloat64InsertLowWord32:
__ FmoveLow(i.OutputDoubleRegister(), i.InputRegister(1));
break;
case kMipsFloat64InsertHighWord32:
__ FmoveHigh(i.OutputDoubleRegister(), i.InputRegister(1));
break;
// ... more basic instructions ...
......
src/compiler/mips/instruction-codes-mips.h
View file @ 7290d15e
......@@ -61,10 +61,10 @@ namespace compiler {
V(MipsSwc1) \
V(MipsLdc1) \
V(MipsSdc1) \
V(MipsFmoveLowUwD) \
V(MipsFmoveLowDUw) \
V(MipsFmoveHighUwD) \
V(MipsFmoveHighDUw) \
V(MipsFloat64ExtractLowWord32) \
V(MipsFloat64ExtractHighWord32) \
V(MipsFloat64InsertLowWord32) \
V(MipsFloat64InsertHighWord32) \
V(MipsPush) \
V(MipsStoreToStackSlot) \
V(MipsStackClaim) \
......
src/compiler/mips/instruction-selector-mips.cc
View file @ 7290d15e
......@@ -902,14 +902,14 @@ void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) {
void InstructionSelector::VisitFloat64ExtractLowWord32(Node* node) {
MipsOperandGenerator g(this);
Emit(kMipsFmoveLowUwD, g.DefineAsRegister(node),
Emit(kMipsFloat64ExtractLowWord32, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) {
MipsOperandGenerator g(this);
Emit(kMipsFmoveHighUwD, g.DefineAsRegister(node),
Emit(kMipsFloat64ExtractHighWord32, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
......@@ -918,8 +918,8 @@ void InstructionSelector::VisitFloat64InsertLowWord32(Node* node) {
MipsOperandGenerator g(this);
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
Emit(kMipsFmoveLowDUw, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseRegister(right));
Emit(kMipsFloat64InsertLowWord32, g.DefineSameAsFirst(node),
g.UseRegister(left), g.UseRegister(right));
}
......@@ -927,8 +927,8 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
MipsOperandGenerator g(this);
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
Emit(kMipsFmoveHighDUw, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseRegister(right));
Emit(kMipsFloat64InsertHighWord32, g.DefineSameAsFirst(node),
g.UseRegister(left), g.UseRegister(right));
}
......
src/compiler/mips64/code-generator-mips64.cc
View file @ 7290d15e
......@@ -685,16 +685,16 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ Trunc_uw_d(i.InputDoubleRegister(0), i.OutputRegister(), scratch);
break;
}
case kMips64FmoveLowUwD:
case kMips64Float64ExtractLowWord32:
__ FmoveLow(i.OutputRegister(), i.InputDoubleRegister(0));
break;
case kMips64FmoveLowDUw:
__ FmoveLow(i.OutputDoubleRegister(), i.InputRegister(1));
break;
case kMips64FmoveHighUwD:
case kMips64Float64ExtractHighWord32:
__ FmoveHigh(i.OutputRegister(), i.InputDoubleRegister(0));
break;
case kMips64FmoveHighDUw:
case kMips64Float64InsertLowWord32:
__ FmoveLow(i.OutputDoubleRegister(), i.InputRegister(1));
break;
case kMips64Float64InsertHighWord32:
__ FmoveHigh(i.OutputDoubleRegister(), i.InputRegister(1));
break;
// ... more basic instructions ...
......
src/compiler/mips64/instruction-codes-mips64.h
View file @ 7290d15e
......@@ -11,78 +11,78 @@ namespace compiler {
// MIPS64-specific opcodes that specify which assembly sequence to emit.
// Most opcodes specify a single instruction.
#define TARGET_ARCH_OPCODE_LIST(V) \
V(Mips64Add) \
V(Mips64Dadd) \
V(Mips64Sub) \
V(Mips64Dsub) \
V(Mips64Mul) \
V(Mips64MulHigh) \
V(Mips64MulHighU) \
V(Mips64Dmul) \
V(Mips64Div) \
V(Mips64Ddiv) \
V(Mips64DivU) \
V(Mips64DdivU) \
V(Mips64Mod) \
V(Mips64Dmod) \
V(Mips64ModU) \
V(Mips64DmodU) \
V(Mips64And) \
V(Mips64Or) \
V(Mips64Xor) \
V(Mips64Shl) \
V(Mips64Shr) \
V(Mips64Sar) \
V(Mips64Ext) \
V(Mips64Dext) \
V(Mips64Dshl) \
V(Mips64Dshr) \
V(Mips64Dsar) \
V(Mips64Ror) \
V(Mips64Dror) \
V(Mips64Mov) \
V(Mips64Tst) \
V(Mips64Tst32) \
V(Mips64Cmp) \
V(Mips64Cmp32) \
V(Mips64CmpD) \
V(Mips64AddD) \
V(Mips64SubD) \
V(Mips64MulD) \
V(Mips64DivD) \
V(Mips64ModD) \
V(Mips64SqrtD) \
V(Mips64Float64RoundDown) \
V(Mips64Float64RoundTruncate) \
V(Mips64Float64RoundUp) \
V(Mips64CvtSD) \
V(Mips64CvtDS) \
V(Mips64TruncWD) \
V(Mips64TruncUwD) \
V(Mips64CvtDW) \
V(Mips64CvtDUw) \
V(Mips64Lb) \
V(Mips64Lbu) \
V(Mips64Sb) \
V(Mips64Lh) \
V(Mips64Lhu) \
V(Mips64Sh) \
V(Mips64Ld) \
V(Mips64Lw) \
V(Mips64Sw) \
V(Mips64Sd) \
V(Mips64Lwc1) \
V(Mips64Swc1) \
V(Mips64Ldc1) \
V(Mips64Sdc1) \
V(Mips64FmoveLowUwD) \
V(Mips64FmoveLowDUw) \
V(Mips64FmoveHighUwD) \
V(Mips64FmoveHighDUw) \
V(Mips64Push) \
V(Mips64StoreToStackSlot) \
V(Mips64StackClaim) \
#define TARGET_ARCH_OPCODE_LIST(V) \
V(Mips64Add) \
V(Mips64Dadd) \
V(Mips64Sub) \
V(Mips64Dsub) \
V(Mips64Mul) \
V(Mips64MulHigh) \
V(Mips64MulHighU) \
V(Mips64Dmul) \
V(Mips64Div) \
V(Mips64Ddiv) \
V(Mips64DivU) \
V(Mips64DdivU) \
V(Mips64Mod) \
V(Mips64Dmod) \
V(Mips64ModU) \
V(Mips64DmodU) \
V(Mips64And) \
V(Mips64Or) \
V(Mips64Xor) \
V(Mips64Shl) \
V(Mips64Shr) \
V(Mips64Sar) \
V(Mips64Ext) \
V(Mips64Dext) \
V(Mips64Dshl) \
V(Mips64Dshr) \
V(Mips64Dsar) \
V(Mips64Ror) \
V(Mips64Dror) \
V(Mips64Mov) \
V(Mips64Tst) \
V(Mips64Tst32) \
V(Mips64Cmp) \
V(Mips64Cmp32) \
V(Mips64CmpD) \
V(Mips64AddD) \
V(Mips64SubD) \
V(Mips64MulD) \
V(Mips64DivD) \
V(Mips64ModD) \
V(Mips64SqrtD) \
V(Mips64Float64RoundDown) \
V(Mips64Float64RoundTruncate) \
V(Mips64Float64RoundUp) \
V(Mips64CvtSD) \
V(Mips64CvtDS) \
V(Mips64TruncWD) \
V(Mips64TruncUwD) \
V(Mips64CvtDW) \
V(Mips64CvtDUw) \
V(Mips64Lb) \
V(Mips64Lbu) \
V(Mips64Sb) \
V(Mips64Lh) \
V(Mips64Lhu) \
V(Mips64Sh) \
V(Mips64Ld) \
V(Mips64Lw) \
V(Mips64Sw) \
V(Mips64Sd) \
V(Mips64Lwc1) \
V(Mips64Swc1) \
V(Mips64Ldc1) \
V(Mips64Sdc1) \
V(Mips64Float64ExtractLowWord32) \
V(Mips64Float64ExtractHighWord32) \
V(Mips64Float64InsertLowWord32) \
V(Mips64Float64InsertHighWord32) \
V(Mips64Push) \
V(Mips64StoreToStackSlot) \
V(Mips64StackClaim) \
V(Mips64StoreWriteBarrier)
......
src/compiler/mips64/instruction-selector-mips64.cc
View file @ 7290d15e
......@@ -1154,14 +1154,14 @@ void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) {
void InstructionSelector::VisitFloat64ExtractLowWord32(Node* node) {
Mips64OperandGenerator g(this);
Emit(kMips64FmoveLowUwD, g.DefineAsRegister(node),
Emit(kMips64Float64ExtractLowWord32, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) {
Mips64OperandGenerator g(this);
Emit(kMips64FmoveHighUwD, g.DefineAsRegister(node),
Emit(kMips64Float64ExtractHighWord32, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
......@@ -1170,8 +1170,8 @@ void InstructionSelector::VisitFloat64InsertLowWord32(Node* node) {
Mips64OperandGenerator g(this);
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
Emit(kMips64FmoveLowDUw, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseRegister(right));
Emit(kMips64Float64InsertLowWord32, g.DefineSameAsFirst(node),
g.UseRegister(left), g.UseRegister(right));
}
......@@ -1179,8 +1179,8 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
Mips64OperandGenerator g(this);
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
Emit(kMips64FmoveHighDUw, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseRegister(right));
Emit(kMips64Float64InsertHighWord32, g.DefineSameAsFirst(node),
g.UseRegister(left), g.UseRegister(right));
}
......
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