PPC: [wasm-simd] Use memory for splatting 64x2 lanes

Change-Id: Iaa0075ea16c289a369b354f2f44b3d1161f2faac
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2273581Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68597}

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -2155,18 +2155,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
 #endif  // V8_TARGET_ARCH_PPC64
     case kPPC_F64x2Splat: {
       Simd128Register dst = i.OutputSimd128Register();
-      constexpr int shift_bits = 64;
-      __ MovDoubleToInt64(r0, i.InputDoubleRegister(0));
-      __ mtvsrd(dst, r0);
-      // right shift
-      __ li(ip, Operand(shift_bits));
-      __ mtvsrd(kScratchDoubleReg, ip);
-      __ vspltb(kScratchDoubleReg, kScratchDoubleReg, Operand(7));
-      __ vsro(dst, dst, kScratchDoubleReg);
-      // reload
-      __ vxor(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
-      __ mtvsrd(kScratchDoubleReg, r0);
-      __ vor(dst, dst, kScratchDoubleReg);
+      __ MovDoubleToInt64(ip, i.InputDoubleRegister(0));
+      // Need to maintain 16 byte alignment for lvx.
+      __ addi(sp, sp, Operand(-24));
+      __ StoreP(ip, MemOperand(sp, 0));
+      __ StoreP(ip, MemOperand(sp, 8));
+      __ li(r0, Operand(0));
+      __ lvx(dst, MemOperand(sp, r0));
+      __ addi(sp, sp, Operand(24));
       break;
     }
     case kPPC_F32x4Splat: {
@@ -2179,17 +2175,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     case kPPC_I64x2Splat: {
       Register src = i.InputRegister(0);
       Simd128Register dst = i.OutputSimd128Register();
-      constexpr int shift_bits = 64;
-      __ mtvsrd(dst, src);
-      // right shift
-      __ li(ip, Operand(shift_bits));
-      __ mtvsrd(kScratchDoubleReg, ip);
-      __ vspltb(kScratchDoubleReg, kScratchDoubleReg, Operand(7));
-      __ vsro(dst, dst, kScratchDoubleReg);
-      // reload
-      __ vxor(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
-      __ mtvsrd(kScratchDoubleReg, src);
-      __ vor(dst, dst, kScratchDoubleReg);
+      // Need to maintain 16 byte alignment for lvx.
+      __ addi(sp, sp, Operand(-24));
+      __ StoreP(src, MemOperand(sp, 0));
+      __ StoreP(src, MemOperand(sp, 8));
+      __ li(r0, Operand(0));
+      __ lvx(dst, MemOperand(sp, r0));
+      __ addi(sp, sp, Operand(24));
       break;
     }
     case kPPC_I32x4Splat: {