[codegen] Add TSAN support for kX64MovqCompressTagged generated code

This CL would finish adding TSAN support for the generated tagged
stores.

Bug: v8:7790, v8:11600
Change-Id: Icaadc06ea740089dadf3d9f86da56d84dad1d4b6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2922113Reviewed-by: Georg Neis <neis@chromium.org>
Commit-Queue: Santiago Aboy Solanes <solanes@chromium.org>
Cr-Commit-Position: refs/heads/master@{#74872}

src/compiler/backend/x64/code-generator-x64.cc

@@ -2186,9 +2186,27 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       size_t index = 0;
       Operand operand = i.MemoryOperand(&index);
       if (HasImmediateInput(instr, index)) {
-        __ StoreTaggedField(operand, i.InputImmediate(index));
+        Immediate value = i.InputImmediate(index);
+#ifdef V8_IS_TSAN
+        Register value_reg = i.TempRegister(1);
+        __ movq(value_reg, value);
+        Register scratch0 = i.TempRegister(0);
+        auto tsan_ool = zone()->New<OutOfLineTSANRelaxedStore>(
+            this, operand, value_reg, scratch0, DetermineStubCallMode());
+        __ jmp(tsan_ool->entry());
+        __ bind(tsan_ool->exit());
+#endif  // V8_IS_TSAN
+        __ StoreTaggedField(operand, value);
       } else {
-        __ StoreTaggedField(operand, i.InputRegister(index));
+        Register value = i.InputRegister(index);
+#ifdef V8_IS_TSAN
+        Register scratch0 = i.TempRegister(0);
+        auto tsan_ool = zone()->New<OutOfLineTSANRelaxedStore>(
+            this, operand, value, scratch0, DetermineStubCallMode());
+        __ jmp(tsan_ool->entry());
+        __ bind(tsan_ool->exit());
+#endif  // V8_IS_TSAN
+        __ StoreTaggedField(operand, value);
       }
       break;
     }

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -506,23 +506,40 @@ void InstructionSelector::VisitStore(Node* node) {
     code |= MiscField::encode(static_cast<int>(record_write_mode));
     Emit(code, 0, nullptr, arraysize(inputs), inputs, arraysize(temps), temps);
   } else {
-    ArchOpcode opcode = GetStoreOpcode(store_rep);
-    InstructionOperand inputs[4];
-    size_t input_count = 0;
-    AddressingMode addressing_mode =
-        g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
-    InstructionCode code =
-        opcode | AddressingModeField::encode(addressing_mode);
     if ((ElementSizeLog2Of(store_rep.representation()) <
          kSystemPointerSizeLog2) &&
         value->opcode() == IrOpcode::kTruncateInt64ToInt32) {
       value = value->InputAt(0);
     }
+#ifdef V8_IS_TSAN
+    // On TSAN builds we require two scratch registers. Because of this we also
+    // have to modify the inputs to take into account possible aliasing and use
+    // UseUniqueRegister which is not required for non-TSAN builds.
+    AddressingMode addressing_mode;
+    InstructionOperand inputs[] = {
+        g.UseUniqueRegister(base),
+        g.GetEffectiveIndexOperand(index, &addressing_mode),
+        g.CanBeImmediate(value) ? g.UseImmediate(value)
+                                : g.UseUniqueRegister(value)};
+    size_t input_count = arraysize(inputs);
+    InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()};
+    size_t temp_count = arraysize(temps);
+#else
+    InstructionOperand inputs[4];
+    size_t input_count = 0;
+    AddressingMode addressing_mode =
+        g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
     InstructionOperand value_operand =
         g.CanBeImmediate(value) ? g.UseImmediate(value) : g.UseRegister(value);
     inputs[input_count++] = value_operand;
+    InstructionOperand* temps = nullptr;
+    size_t temp_count = 0;
+#endif  // V8_IS_TSAN
+    ArchOpcode opcode = GetStoreOpcode(store_rep);
+    InstructionCode code =
+        opcode | AddressingModeField::encode(addressing_mode);
     Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count,
-         inputs);
+         inputs, temp_count, temps);
   }
 }