s390x: rename Mul/Div/Mod operations

Change-Id: Icf959a6e3ac66a5e907379ee9fec25223517af51
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2598696Reviewed-by: Milad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71841}

src/builtins/s390/builtins-s390.cc

@@ -1602,7 +1602,7 @@ void Generate_ContinueToBuiltinHelper(MacroAssembler* masm,
     __ StoreU64(scratch, MemOperand(sp, r1));
     // Recover arguments count.
     __ SubS64(r2, r2,
-            Operand(BuiltinContinuationFrameConstants::kFixedSlotCount));
+              Operand(BuiltinContinuationFrameConstants::kFixedSlotCount));
   }
   __ LoadP(
       fp,
@@ -2576,8 +2576,8 @@ void Builtins::Generate_ArgumentsAdaptorTrampoline(MacroAssembler* masm) {
       __ SubS64(r6, fp, r1);
       // Adjust for frame.
       __ SubS64(r6, r6,
-              Operand(ArgumentsAdaptorFrameConstants::kFixedFrameSizeFromFp +
-                      kSystemPointerSize));
+                Operand(ArgumentsAdaptorFrameConstants::kFixedFrameSizeFromFp +
+                        kSystemPointerSize));
 
       Label fill;
       __ bind(&fill);

src/codegen/s390/macro-assembler-s390.cc

@@ -1528,7 +1528,7 @@ void MacroAssembler::InvokePrologue(Register expected_parameter_count,
   // If overapplication or if the actual argument count is equal to the
   // formal parameter count, no need to push extra undefined values.
   SubS64(expected_parameter_count, expected_parameter_count,
-       actual_parameter_count);
+         actual_parameter_count);
   ble(&regular_invoke);
 
   Label stack_overflow;
@@ -1918,6 +1918,10 @@ void TurboAssembler::Assert(Condition cond, AbortReason reason, CRegister cr) {
   if (emit_debug_code()) Check(cond, reason, cr);
 }
 
+void TurboAssembler::AssertUnreachable(AbortReason reason) {
+  if (emit_debug_code()) Abort(reason);
+}
+
 void TurboAssembler::Check(Condition cond, AbortReason reason, CRegister cr) {
   Label L;
   b(cond, &L);
@@ -2334,7 +2338,7 @@ void TurboAssembler::mov(Register dst, const Operand& src) {
   iilf(dst, Operand(lo_32));
 }
 
-void TurboAssembler::Mul32(Register dst, const MemOperand& src1) {
+void TurboAssembler::MulS32(Register dst, const MemOperand& src1) {
   if (is_uint12(src1.offset())) {
     ms(dst, src1);
   } else if (is_int20(src1.offset())) {
@@ -2344,9 +2348,9 @@ void TurboAssembler::Mul32(Register dst, const MemOperand& src1) {
   }
 }
 
-void TurboAssembler::Mul32(Register dst, Register src1) { msr(dst, src1); }
+void TurboAssembler::MulS32(Register dst, Register src1) { msr(dst, src1); }
 
-void TurboAssembler::Mul32(Register dst, const Operand& src1) {
+void TurboAssembler::MulS32(Register dst, const Operand& src1) {
   msfi(dst, src1);
 }
 
@@ -2357,20 +2361,20 @@ void TurboAssembler::Mul32(Register dst, const Operand& src1) {
     srlg(dst, dst, Operand(32));  \
   }
 
-void TurboAssembler::MulHigh32(Register dst, Register src1,
-                               const MemOperand& src2) {
+void TurboAssembler::MulHighS32(Register dst, Register src1,
+                                const MemOperand& src2) {
   Generate_MulHigh32(msgf);
 }
 
-void TurboAssembler::MulHigh32(Register dst, Register src1, Register src2) {
+void TurboAssembler::MulHighS32(Register dst, Register src1, Register src2) {
   if (dst == src2) {
     std::swap(src1, src2);
   }
   Generate_MulHigh32(msgfr);
 }
 
-void TurboAssembler::MulHigh32(Register dst, Register src1,
-                               const Operand& src2) {
+void TurboAssembler::MulHighS32(Register dst, Register src1,
+                                const Operand& src2) {
   Generate_MulHigh32(msgfi);
 }
 
@@ -2432,45 +2436,6 @@ void TurboAssembler::Mul32WithOverflowIfCCUnequal(Register dst, Register src1,
 
 #undef Generate_Mul32WithOverflowIfCCUnequal
 
-void TurboAssembler::Mul64(Register dst, const MemOperand& src1) {
-  if (is_int20(src1.offset())) {
-    msg(dst, src1);
-  } else {
-    UNIMPLEMENTED();
-  }
-}
-
-void TurboAssembler::Mul64(Register dst, Register src1) { msgr(dst, src1); }
-
-void TurboAssembler::Mul64(Register dst, const Operand& src1) {
-  msgfi(dst, src1);
-}
-
-void TurboAssembler::Mul(Register dst, Register src1, Register src2) {
-  if (CpuFeatures::IsSupported(MISC_INSTR_EXT2)) {
-    MulPWithCondition(dst, src1, src2);
-  } else {
-    if (dst == src2) {
-      MulP(dst, src1);
-    } else if (dst == src1) {
-      MulP(dst, src2);
-    } else {
-      Move(dst, src1);
-      MulP(dst, src2);
-    }
-  }
-}
-
-void TurboAssembler::DivP(Register dividend, Register divider) {
-  // have to make sure the src and dst are reg pairs
-  DCHECK_EQ(dividend.code() % 2, 0);
-#if V8_TARGET_ARCH_S390X
-  dsgr(dividend, divider);
-#else
-  dr(dividend, divider);
-#endif
-}
-
 #define Generate_Div32(instr) \
   {                           \
     lgfr(r1, src1);           \
@@ -2478,12 +2443,12 @@ void TurboAssembler::DivP(Register dividend, Register divider) {
     LoadU32(dst, r1);          \
   }
 
-void TurboAssembler::Div32(Register dst, Register src1,
-                           const MemOperand& src2) {
+void TurboAssembler::DivS32(Register dst, Register src1,
+                            const MemOperand& src2) {
   Generate_Div32(dsgf);
 }
 
-void TurboAssembler::Div32(Register dst, Register src1, Register src2) {
+void TurboAssembler::DivS32(Register dst, Register src1, Register src2) {
   Generate_Div32(dsgfr);
 }
 
@@ -2515,12 +2480,12 @@ void TurboAssembler::DivU32(Register dst, Register src1, Register src2) {
     lgr(dst, r1);             \
   }
 
-void TurboAssembler::Div64(Register dst, Register src1,
-                           const MemOperand& src2) {
+void TurboAssembler::DivS64(Register dst, Register src1,
+                            const MemOperand& src2) {
   Generate_Div64(dsg);
 }
 
-void TurboAssembler::Div64(Register dst, Register src1, Register src2) {
+void TurboAssembler::DivS64(Register dst, Register src1, Register src2) {
   Generate_Div64(dsgr);
 }
 
@@ -2552,12 +2517,12 @@ void TurboAssembler::DivU64(Register dst, Register src1, Register src2) {
     LoadU32(dst, r0);          \
   }
 
-void TurboAssembler::Mod32(Register dst, Register src1,
-                           const MemOperand& src2) {
+void TurboAssembler::ModS32(Register dst, Register src1,
+                            const MemOperand& src2) {
   Generate_Mod32(dsgf);
 }
 
-void TurboAssembler::Mod32(Register dst, Register src1, Register src2) {
+void TurboAssembler::ModS32(Register dst, Register src1, Register src2) {
   Generate_Mod32(dsgfr);
 }
 
@@ -2589,12 +2554,12 @@ void TurboAssembler::ModU32(Register dst, Register src1, Register src2) {
     lgr(dst, r0);             \
   }
 
-void TurboAssembler::Mod64(Register dst, Register src1,
-                           const MemOperand& src2) {
+void TurboAssembler::ModS64(Register dst, Register src1,
+                            const MemOperand& src2) {
   Generate_Mod64(dsg);
 }
 
-void TurboAssembler::Mod64(Register dst, Register src1, Register src2) {
+void TurboAssembler::ModS64(Register dst, Register src1, Register src2) {
   Generate_Mod64(dsgr);
 }
 
@@ -2619,34 +2584,13 @@ void TurboAssembler::ModU64(Register dst, Register src1, Register src2) {
 
 #undef Generate_ModU64
 
-void TurboAssembler::MulP(Register dst, const Operand& opnd) {
-#if V8_TARGET_ARCH_S390X
+void TurboAssembler::MulS64(Register dst, const Operand& opnd) {
   msgfi(dst, opnd);
-#else
-  msfi(dst, opnd);
-#endif
-}
-
-void TurboAssembler::MulP(Register dst, Register src) {
-#if V8_TARGET_ARCH_S390X
-  msgr(dst, src);
-#else
-  msr(dst, src);
-#endif
 }
 
-void TurboAssembler::MulPWithCondition(Register dst, Register src1,
-                                       Register src2) {
-  CHECK(CpuFeatures::IsSupported(MISC_INSTR_EXT2));
-#if V8_TARGET_ARCH_S390X
-  msgrkc(dst, src1, src2);
-#else
-  msrkc(dst, src1, src2);
-#endif
-}
+void TurboAssembler::MulS64(Register dst, Register src) { msgr(dst, src); }
 
-void TurboAssembler::MulP(Register dst, const MemOperand& opnd) {
-#if V8_TARGET_ARCH_S390X
+void TurboAssembler::MulS64(Register dst, const MemOperand& opnd) {
   if (is_uint16(opnd.offset())) {
     ms(dst, opnd);
   } else if (is_int20(opnd.offset())) {
@@ -2654,13 +2598,6 @@ void TurboAssembler::MulP(Register dst, const MemOperand& opnd) {
   } else {
     UNIMPLEMENTED();
   }
-#else
-  if (is_int20(opnd.offset())) {
-    msg(dst, opnd);
-  } else {
-    UNIMPLEMENTED();
-  }
-#endif
 }
 
 void TurboAssembler::Sqrt(DoubleRegister result, DoubleRegister input) {

src/codegen/s390/macro-assembler-s390.h

@@ -232,16 +232,45 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void SubU32(Register dst, Register src1, Register src2);
 
   // Multiply
-  void MulP(Register dst, const Operand& opnd);
-  void MulP(Register dst, Register src);
-  void MulP(Register dst, const MemOperand& opnd);
-  void Mul(Register dst, Register src1, Register src2);
-  void Mul32(Register dst, const MemOperand& src1);
-  void Mul32(Register dst, Register src1);
-  void Mul32(Register dst, const Operand& src1);
-  void MulHigh32(Register dst, Register src1, const MemOperand& src2);
-  void MulHigh32(Register dst, Register src1, Register src2);
-  void MulHigh32(Register dst, Register src1, const Operand& src2);
+  void MulS64(Register dst, const Operand& opnd);
+  void MulS64(Register dst, Register src);
+  void MulS64(Register dst, const MemOperand& opnd);
+  void MulS64(Register dst, Register src1, Register src2) {
+    if (CpuFeatures::IsSupported(MISC_INSTR_EXT2)) {
+      msgrkc(dst, src1, src2);
+    } else {
+      if (dst == src2) {
+        MulS64(dst, src1);
+      } else if (dst == src1) {
+        MulS64(dst, src2);
+      } else {
+        mov(dst, src1);
+        MulS64(dst, src2);
+      }
+    }
+  }
+
+  void MulS32(Register dst, const MemOperand& src1);
+  void MulS32(Register dst, Register src1);
+  void MulS32(Register dst, const Operand& src1);
+  void MulS32(Register dst, Register src1, Register src2) {
+    if (CpuFeatures::IsSupported(MISC_INSTR_EXT2)) {
+      msrkc(dst, src1, src2);
+    } else {
+      if (dst == src2) {
+        MulS32(dst, src1);
+      } else if (dst == src1) {
+        MulS32(dst, src2);
+      } else {
+        mov(dst, src1);
+        MulS32(dst, src2);
+      }
+    }
+  }
+
+  void MulHighS32(Register dst, Register src1, const MemOperand& src2);
+  void MulHighS32(Register dst, Register src1, Register src2);
+  void MulHighS32(Register dst, Register src1, const Operand& src2);
   void MulHighU32(Register dst, Register src1, const MemOperand& src2);
   void MulHighU32(Register dst, Register src1, Register src2);
   void MulHighU32(Register dst, Register src1, const Operand& src2);
@@ -250,29 +279,23 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void Mul32WithOverflowIfCCUnequal(Register dst, Register src1, Register src2);
   void Mul32WithOverflowIfCCUnequal(Register dst, Register src1,
                                     const Operand& src2);
-  void Mul64(Register dst, const MemOperand& src1);
-  void Mul64(Register dst, Register src1);
-  void Mul64(Register dst, const Operand& src1);
-  void MulPWithCondition(Register dst, Register src1, Register src2);
-
   // Divide
-  void DivP(Register dividend, Register divider);
-  void Div32(Register dst, Register src1, const MemOperand& src2);
-  void Div32(Register dst, Register src1, Register src2);
+  void DivS32(Register dst, Register src1, const MemOperand& src2);
+  void DivS32(Register dst, Register src1, Register src2);
   void DivU32(Register dst, Register src1, const MemOperand& src2);
   void DivU32(Register dst, Register src1, Register src2);
-  void Div64(Register dst, Register src1, const MemOperand& src2);
-  void Div64(Register dst, Register src1, Register src2);
+  void DivS64(Register dst, Register src1, const MemOperand& src2);
+  void DivS64(Register dst, Register src1, Register src2);
   void DivU64(Register dst, Register src1, const MemOperand& src2);
   void DivU64(Register dst, Register src1, Register src2);
 
   // Mod
-  void Mod32(Register dst, Register src1, const MemOperand& src2);
-  void Mod32(Register dst, Register src1, Register src2);
+  void ModS32(Register dst, Register src1, const MemOperand& src2);
+  void ModS32(Register dst, Register src1, Register src2);
   void ModU32(Register dst, Register src1, const MemOperand& src2);
   void ModU32(Register dst, Register src1, Register src2);
-  void Mod64(Register dst, Register src1, const MemOperand& src2);
-  void Mod64(Register dst, Register src1, Register src2);
+  void ModS64(Register dst, Register src1, const MemOperand& src2);
+  void ModS64(Register dst, Register src1, Register src2);
   void ModU64(Register dst, Register src1, const MemOperand& src2);
   void ModU64(Register dst, Register src1, Register src2);
 
@@ -791,6 +814,10 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   // Use --debug_code to enable.
   void Assert(Condition cond, AbortReason reason, CRegister cr = cr7);
 
+  // Like Assert(), but without condition.
+  // Use --debug-code to enable.
+  void AssertUnreachable(AbortReason reason);
+
   // Like Assert(), but always enabled.
   void Check(Condition cond, AbortReason reason, CRegister cr = cr7);
 

src/compiler/backend/s390/code-generator-s390.cc

@@ -1719,9 +1719,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     case kS390_Mul32:
       // zero-ext
       if (CpuFeatures::IsSupported(MISC_INSTR_EXT2)) {
-        ASSEMBLE_BIN32_OP(RRRInstr(msrkc), RM32Instr(msc), RIInstr(Mul32));
+        ASSEMBLE_BIN32_OP(RRRInstr(msrkc), RM32Instr(msc), RIInstr(MulS32));
       } else {
-        ASSEMBLE_BIN32_OP(RRInstr(Mul32), RM32Instr(Mul32), RIInstr(Mul32));
+        ASSEMBLE_BIN32_OP(RRInstr(MulS32), RM32Instr(MulS32), RIInstr(MulS32));
       }
       break;
     case kS390_Mul32WithOverflow:
@@ -1731,12 +1731,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                         RRIInstr(Mul32WithOverflowIfCCUnequal));
       break;
     case kS390_Mul64:
-      ASSEMBLE_BIN_OP(RRInstr(Mul64), RM64Instr(Mul64), RIInstr(Mul64));
+      ASSEMBLE_BIN_OP(RRInstr(MulS64), RM64Instr(MulS64), RIInstr(MulS64));
       break;
     case kS390_MulHigh32:
       // zero-ext
-      ASSEMBLE_BIN_OP(RRRInstr(MulHigh32), RRM32Instr(MulHigh32),
-                      RRIInstr(MulHigh32));
+      ASSEMBLE_BIN_OP(RRRInstr(MulHighS32), RRM32Instr(MulHighS32),
+                      RRIInstr(MulHighS32));
       break;
     case kS390_MulHighU32:
       // zero-ext
@@ -1750,11 +1750,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       ASSEMBLE_BIN_OP(DDInstr(mdbr), DMTInstr(MulFloat64), nullInstr);
       break;
     case kS390_Div64:
-      ASSEMBLE_BIN_OP(RRRInstr(Div64), RRM64Instr(Div64), nullInstr);
+      ASSEMBLE_BIN_OP(RRRInstr(DivS64), RRM64Instr(DivS64), nullInstr);
       break;
     case kS390_Div32: {
       // zero-ext
-      ASSEMBLE_BIN_OP(RRRInstr(Div32), RRM32Instr(Div32), nullInstr);
+      ASSEMBLE_BIN_OP(RRRInstr(DivS32), RRM32Instr(DivS32), nullInstr);
       break;
     }
     case kS390_DivU64:
@@ -1773,14 +1773,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     case kS390_Mod32:
       // zero-ext
-      ASSEMBLE_BIN_OP(RRRInstr(Mod32), RRM32Instr(Mod32), nullInstr);
+      ASSEMBLE_BIN_OP(RRRInstr(ModS32), RRM32Instr(ModS32), nullInstr);
       break;
     case kS390_ModU32:
       // zero-ext
       ASSEMBLE_BIN_OP(RRRInstr(ModU32), RRM32Instr(ModU32), nullInstr);
       break;
     case kS390_Mod64:
-      ASSEMBLE_BIN_OP(RRRInstr(Mod64), RRM64Instr(Mod64), nullInstr);
+      ASSEMBLE_BIN_OP(RRRInstr(ModS64), RRM64Instr(ModS64), nullInstr);
       break;
     case kS390_ModU64:
       ASSEMBLE_BIN_OP(RRRInstr(ModU64), RRM64Instr(ModU64), nullInstr);
@@ -3032,7 +3032,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       for (int i = 0; i < 2; i++) {
         __ vlgv(scratch_0, src0, MemOperand(r0, i), Condition(3));
         __ vlgv(scratch_1, src1, MemOperand(r0, i), Condition(3));
-        __ Mul64(scratch_0, scratch_1);
+        __ MulS64(scratch_0, scratch_1);
         scratch_0 = r1;
         scratch_1 = ip;
       }
@@ -4124,7 +4124,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     __ vlgv(scratch_0, kScratchDoubleReg, MemOperand(r0, lane), Condition(3)); \
     __ vlgv(scratch_1, i.OutputSimd128Register(), MemOperand(r0, lane),        \
             Condition(3));                                                     \
-    __ Mul64(scratch_0, scratch_1);                                            \
+    __ MulS64(scratch_0, scratch_1);                                           \
     scratch_0 = r1;                                                            \
     scratch_1 = ip;                                                            \
   }                                                                            \