[mips32] Fix Float64 Abs operation

The lower 32 bits of output FPURegister is undefined now, this CL
copies the input FPURegister's lower 32 bits to output FPURegister.

Change-Id: I10c078fafeddd5de207ced4f7c01f35d32999733
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2449153Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#70302}

src/compiler/backend/mips/code-generator-mips.cc

@@ -1336,15 +1336,19 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ MovFromFloatResult(i.OutputDoubleRegister());
       break;
     }
-    case kMipsAbsD:
+    case kMipsAbsD: {
+      FPURegister src = i.InputDoubleRegister(0);
+      FPURegister dst = i.OutputDoubleRegister();
       if (IsMipsArchVariant(kMips32r6)) {
-        __ abs_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
+        __ abs_d(dst, src);
       } else {
-        __ mfhc1(kScratchReg, i.InputDoubleRegister(0));
+        __ Move(dst, src);
+        __ mfhc1(kScratchReg, src);
         __ Ins(kScratchReg, zero_reg, 31, 1);
-        __ mthc1(kScratchReg, i.OutputDoubleRegister());
+        __ mthc1(kScratchReg, dst);
       }
       break;
+    }
     case kMipsNegS:
       __ Neg_s(i.OutputSingleRegister(), i.InputSingleRegister(0));
       break;