Commit 42734165 authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot

[wasm-simd] Add AVX for pextrq

Bug: v8:9561
Change-Id: I2259e72829c0ad688284dcecef8aaf418ad53022
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1980503Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65643}
parent 30b48201
...@@ -1435,6 +1435,11 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { ...@@ -1435,6 +1435,11 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
vinstr(0x16, src, xmm0, dst, k66, k0F3A, kW0); vinstr(0x16, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8); emit(imm8);
} }
void vpextrq(Register dst, XMMRegister src, int8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x16, src, xmm0, idst, k66, k0F3A, kW1);
emit(imm8);
}
void vpinsrb(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) { void vpinsrb(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
XMMRegister isrc = XMMRegister::from_code(src2.code()); XMMRegister isrc = XMMRegister::from_code(src2.code());
vinstr(0x20, dst, src1, isrc, k66, k0F3A, kW0); vinstr(0x20, dst, src1, isrc, k66, k0F3A, kW0);
......
...@@ -234,6 +234,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { ...@@ -234,6 +234,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP_SSE4_1(Pmovzxbw, pmovzxbw) AVX_OP_SSE4_1(Pmovzxbw, pmovzxbw)
AVX_OP_SSE4_1(Pmovzxwd, pmovzxwd) AVX_OP_SSE4_1(Pmovzxwd, pmovzxwd)
AVX_OP_SSE4_1(Pmovzxdq, pmovzxdq) AVX_OP_SSE4_1(Pmovzxdq, pmovzxdq)
AVX_OP_SSE4_1(Pextrq, pextrq)
#undef AVX_OP #undef AVX_OP
......
...@@ -2317,8 +2317,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2317,8 +2317,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
} }
case kX64F64x2ExtractLane: { case kX64F64x2ExtractLane: {
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pextrq(kScratchRegister, i.InputSimd128Register(0), i.InputInt8(1)); __ Pextrq(kScratchRegister, i.InputSimd128Register(0), i.InputInt8(1));
__ movq(i.OutputDoubleRegister(), kScratchRegister); __ Movq(i.OutputDoubleRegister(), kScratchRegister);
break; break;
} }
case kX64F64x2Sqrt: { case kX64F64x2Sqrt: {
...@@ -2641,7 +2641,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2641,7 +2641,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
} }
case kX64I64x2ExtractLane: { case kX64I64x2ExtractLane: {
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pextrq(i.OutputRegister(), i.InputSimd128Register(0), i.InputInt8(1)); __ Pextrq(i.OutputRegister(), i.InputSimd128Register(0), i.InputInt8(1));
break; break;
} }
case kX64I64x2ReplaceLane: { case kX64I64x2ReplaceLane: {
......
...@@ -970,7 +970,7 @@ int DisassemblerX64::AVXInstruction(byte* data) { ...@@ -970,7 +970,7 @@ int DisassemblerX64::AVXInstruction(byte* data) {
AppendToBuffer(",%s,0x%x,", NameOfXMMRegister(regop), *current++); AppendToBuffer(",%s,0x%x,", NameOfXMMRegister(regop), *current++);
break; break;
case 0x16: case 0x16:
AppendToBuffer("vpextrd "); AppendToBuffer("vpextr%c ", rex_w() ? 'q' : 'd');
current += PrintRightOperand(current); current += PrintRightOperand(current);
AppendToBuffer(",%s,0x%x,", NameOfXMMRegister(regop), *current++); AppendToBuffer(",%s,0x%x,", NameOfXMMRegister(regop), *current++);
break; break;
......
...@@ -765,6 +765,7 @@ TEST(DisasmX64) { ...@@ -765,6 +765,7 @@ TEST(DisasmX64) {
__ vpextrw(Operand(rbx, rcx, times_4, 10000), xmm2, 5); __ vpextrw(Operand(rbx, rcx, times_4, 10000), xmm2, 5);
__ vpextrd(rax, xmm2, 2); __ vpextrd(rax, xmm2, 2);
__ vpextrd(Operand(rbx, rcx, times_4, 10000), xmm2, 2); __ vpextrd(Operand(rbx, rcx, times_4, 10000), xmm2, 2);
__ vpextrq(rax, xmm2, 2);
__ vpinsrb(xmm1, xmm2, rax, 12); __ vpinsrb(xmm1, xmm2, rax, 12);
__ vpinsrb(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 12); __ vpinsrb(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 12);
......
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