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Commit 3bc8d2a8 authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot
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[wasm][cleanup] Add and use helper to refer to temp Simd128 register 

Bug: v8:9396
Change-Id: Ic183418c83367efe430396bd39a02fa900c193d2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1764488Reviewed-by: 's avatarBill Budge <bbudge@chromium.org>
Reviewed-by: 's avatarMichael Starzinger <mstarzinger@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#63382}
parent 9284d8d8
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Showing with 91 additions and 87 deletions
src/compiler/backend/arm/code-generator-arm.cc
View file @ 3bc8d2a8
......@@ -1903,14 +1903,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmI32x4Shl: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon32, tmp, i.InputRegister(1));
__ vshl(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
tmp);
break;
}
case kArmI32x4ShrS: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon32, tmp, i.InputRegister(1));
__ vneg(Neon32, tmp, tmp);
__ vshl(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
......@@ -1982,7 +1982,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmI32x4ShrU: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon32, tmp, i.InputRegister(1));
__ vneg(Neon32, tmp, tmp);
__ vshl(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
......@@ -2038,14 +2038,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmI16x8Shl: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon16, tmp, i.InputRegister(1));
__ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
tmp);
break;
}
case kArmI16x8ShrS: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon16, tmp, i.InputRegister(1));
__ vneg(Neon16, tmp, tmp);
__ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
......@@ -2126,7 +2126,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmI16x8ShrU: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon16, tmp, i.InputRegister(1));
__ vneg(Neon16, tmp, tmp);
__ vshl(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
......@@ -2185,14 +2185,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmI8x16Shl: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon8, tmp, i.InputRegister(1));
__ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
tmp);
break;
}
case kArmI8x16ShrS: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon8, tmp, i.InputRegister(1));
__ vneg(Neon8, tmp, tmp);
__ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
......@@ -2259,7 +2259,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmI8x16ShrU: {
QwNeonRegister tmp = i.ToSimd128Register(instr->TempAt(0));
QwNeonRegister tmp = i.TempSimd128Register(0);
__ vdup(Neon8, tmp, i.InputRegister(1));
__ vneg(Neon8, tmp, tmp);
__ vshl(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
......
src/compiler/backend/arm64/code-generator-arm64.cc
View file @ 3bc8d2a8
......@@ -1868,14 +1868,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
SIMD_UNOP_CASE(kArm64I64x2Neg, Neg, 2D);
case kArm64I64x2Shl: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V2D(), i.InputRegister64(1));
__ Sshl(i.OutputSimd128Register().V2D(), i.InputSimd128Register(0).V2D(),
tmp.V2D());
break;
}
case kArm64I64x2ShrS: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V2D(), i.InputRegister64(1));
__ Neg(tmp.V2D(), tmp.V2D());
__ Sshl(i.OutputSimd128Register().V2D(), i.InputSimd128Register(0).V2D(),
......@@ -1895,7 +1895,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_BINOP_CASE(kArm64I64x2GtS, Cmgt, 2D);
SIMD_BINOP_CASE(kArm64I64x2GeS, Cmge, 2D);
case kArm64I64x2ShrU: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V2D(), i.InputRegister64(1));
__ Neg(tmp.V2D(), tmp.V2D());
__ Ushl(i.OutputSimd128Register().V2D(), i.InputSimd128Register(0).V2D(),
......@@ -1927,14 +1927,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_WIDENING_UNOP_CASE(kArm64I32x4SConvertI16x8High, Sxtl2, 4S, 8H);
SIMD_UNOP_CASE(kArm64I32x4Neg, Neg, 4S);
case kArm64I32x4Shl: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V4S(), i.InputRegister32(1));
__ Sshl(i.OutputSimd128Register().V4S(), i.InputSimd128Register(0).V4S(),
tmp.V4S());
break;
}
case kArm64I32x4ShrS: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V4S(), i.InputRegister32(1));
__ Neg(tmp.V4S(), tmp.V4S());
__ Sshl(i.OutputSimd128Register().V4S(), i.InputSimd128Register(0).V4S(),
......@@ -1961,7 +1961,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_WIDENING_UNOP_CASE(kArm64I32x4UConvertI16x8Low, Uxtl, 4S, 4H);
SIMD_WIDENING_UNOP_CASE(kArm64I32x4UConvertI16x8High, Uxtl2, 4S, 8H);
case kArm64I32x4ShrU: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V4S(), i.InputRegister32(1));
__ Neg(tmp.V4S(), tmp.V4S());
__ Ushl(i.OutputSimd128Register().V4S(), i.InputSimd128Register(0).V4S(),
......@@ -1994,14 +1994,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_WIDENING_UNOP_CASE(kArm64I16x8SConvertI8x16High, Sxtl2, 8H, 16B);
SIMD_UNOP_CASE(kArm64I16x8Neg, Neg, 8H);
case kArm64I16x8Shl: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V8H(), i.InputRegister32(1));
__ Sshl(i.OutputSimd128Register().V8H(), i.InputSimd128Register(0).V8H(),
tmp.V8H());
break;
}
case kArm64I16x8ShrS: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V8H(), i.InputRegister32(1));
__ Neg(tmp.V8H(), tmp.V8H());
__ Sshl(i.OutputSimd128Register().V8H(), i.InputSimd128Register(0).V8H(),
......@@ -2050,7 +2050,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArm64I16x8ShrU: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V8H(), i.InputRegister32(1));
__ Neg(tmp.V8H(), tmp.V8H());
__ Ushl(i.OutputSimd128Register().V8H(), i.InputSimd128Register(0).V8H(),
......@@ -2097,14 +2097,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
SIMD_UNOP_CASE(kArm64I8x16Neg, Neg, 16B);
case kArm64I8x16Shl: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V16B(), i.InputRegister32(1));
__ Sshl(i.OutputSimd128Register().V16B(),
i.InputSimd128Register(0).V16B(), tmp.V16B());
break;
}
case kArm64I8x16ShrS: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V16B(), i.InputRegister32(1));
__ Neg(tmp.V16B(), tmp.V16B());
__ Sshl(i.OutputSimd128Register().V16B(),
......@@ -2143,7 +2143,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_BINOP_CASE(kArm64I8x16GtS, Cmgt, 16B);
SIMD_BINOP_CASE(kArm64I8x16GeS, Cmge, 16B);
case kArm64I8x16ShrU: {
VRegister tmp = i.ToSimd128Register(instr->TempAt(0));
VRegister tmp = i.TempSimd128Register(0);
__ Dup(tmp.V16B(), i.InputRegister32(1));
__ Neg(tmp.V16B(), tmp.V16B());
__ Ushl(i.OutputSimd128Register().V16B(),
......
src/compiler/backend/code-generator-impl.h
View file @ 3bc8d2a8
......@@ -116,6 +116,10 @@ class InstructionOperandConverter {
return ToSimd128Register(instr_->Output());
}
Simd128Register TempSimd128Register(size_t index) {
return ToSimd128Register(instr_->TempAt(index));
}
// -- Conversions for operands -----------------------------------------------
Label* ToLabel(InstructionOperand* op) {
......
src/compiler/backend/ia32/code-generator-ia32.cc
View file @ 3bc8d2a8
......@@ -2195,28 +2195,28 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kSSEI32x4Shl: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ pslld(i.OutputSimd128Register(), tmp);
break;
}
case kAVXI32x4Shl: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ vpslld(i.OutputSimd128Register(), i.InputSimd128Register(0), tmp);
break;
}
case kSSEI32x4ShrS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ psrad(i.OutputSimd128Register(), tmp);
break;
}
case kAVXI32x4ShrS: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ vpsrad(i.OutputSimd128Register(), i.InputSimd128Register(0), tmp);
break;
......@@ -2350,7 +2350,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
// NAN->0, negative->0
__ pxor(kScratchDoubleReg, kScratchDoubleReg);
__ maxps(dst, kScratchDoubleReg);
......@@ -2378,7 +2378,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
// NAN->0, negative->0
__ vpxor(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
__ vmaxps(dst, dst, kScratchDoubleReg);
......@@ -2413,14 +2413,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kSSEI32x4ShrU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ psrld(i.OutputSimd128Register(), tmp);
break;
}
case kAVXI32x4ShrU: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ vpsrld(i.OutputSimd128Register(), i.InputSimd128Register(0), tmp);
break;
......@@ -2536,28 +2536,28 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kSSEI16x8Shl: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ psllw(i.OutputSimd128Register(), tmp);
break;
}
case kAVXI16x8Shl: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ vpsllw(i.OutputSimd128Register(), i.InputSimd128Register(0), tmp);
break;
}
case kSSEI16x8ShrS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ psraw(i.OutputSimd128Register(), tmp);
break;
}
case kAVXI16x8ShrS: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ vpsraw(i.OutputSimd128Register(), i.InputSimd128Register(0), tmp);
break;
......@@ -2728,14 +2728,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kSSEI16x8ShrU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ psrlw(i.OutputSimd128Register(), tmp);
break;
}
case kAVXI16x8ShrU: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ movd(tmp, i.InputRegister(1));
__ vpsrlw(i.OutputSimd128Register(), i.InputSimd128Register(0), tmp);
break;
......@@ -2902,7 +2902,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
DCHECK_EQ(dst, i.InputSimd128Register(0));
Register shift = i.InputRegister(1);
Register tmp = i.ToRegister(instr->TempAt(0));
XMMRegister tmp_simd = i.ToSimd128Register(instr->TempAt(1));
XMMRegister tmp_simd = i.TempSimd128Register(1);
// Mask off the unwanted bits before word-shifting.
__ pcmpeqw(kScratchDoubleReg, kScratchDoubleReg);
__ mov(tmp, shift);
......@@ -2921,7 +2921,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
XMMRegister src = i.InputSimd128Register(0);
Register shift = i.InputRegister(1);
Register tmp = i.ToRegister(instr->TempAt(0));
XMMRegister tmp_simd = i.ToSimd128Register(instr->TempAt(1));
XMMRegister tmp_simd = i.TempSimd128Register(1);
// Mask off the unwanted bits before word-shifting.
__ vpcmpeqw(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
__ mov(tmp, shift);
......@@ -2938,7 +2938,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
XMMRegister dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
Register tmp = i.ToRegister(instr->TempAt(0));
XMMRegister tmp_simd = i.ToSimd128Register(instr->TempAt(1));
XMMRegister tmp_simd = i.TempSimd128Register(1);
// Unpack the bytes into words, do arithmetic shifts, and repack.
__ punpckhbw(kScratchDoubleReg, dst);
__ punpcklbw(dst, dst);
......@@ -2998,7 +2998,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
XMMRegister dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
XMMRegister right = i.InputSimd128Register(1);
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
// I16x8 view of I8x16
// left = AAaa AAaa ... AAaa AAaa
......@@ -3038,7 +3038,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
XMMRegister dst = i.OutputSimd128Register();
XMMRegister left = i.InputSimd128Register(0);
XMMRegister right = i.InputSimd128Register(1);
XMMRegister tmp = i.ToSimd128Register(instr->TempAt(0));
XMMRegister tmp = i.TempSimd128Register(0);
// I16x8 view of I8x16
// left = AAaa AAaa ... AAaa AAaa
......@@ -3202,7 +3202,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister dst = i.OutputSimd128Register();
Register tmp = i.ToRegister(instr->TempAt(0));
XMMRegister tmp_simd = i.ToSimd128Register(instr->TempAt(1));
XMMRegister tmp_simd = i.TempSimd128Register(1);
// Unpack the bytes into words, do logical shifts, and repack.
__ punpckhbw(kScratchDoubleReg, dst);
__ punpcklbw(dst, dst);
......
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